diff options
author | Tony Lindgren <tony@atomide.com> | 2009-05-26 17:41:35 -0400 |
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committer | Tony Lindgren <tony@atomide.com> | 2009-05-26 17:41:35 -0400 |
commit | 88b6f7eb9b4a06fbfe27f2d98e249577f4cfdaef (patch) | |
tree | 9ef0d7ecd3e0551ca4d13ac0134aeb3ecd8558c7 /arch/arm/plat-omap/sram.c | |
parent | 8f9ccfeeb2cecb54dd093119291ab271ab0fd94a (diff) | |
parent | 7971687094ef48695aa56a0c03416b609bd4d1fd (diff) |
Merge branch 'omap-clock-upstream' of git://git.pwsan.com/linux-2.6 into for-next
Diffstat (limited to 'arch/arm/plat-omap/sram.c')
-rw-r--r-- | arch/arm/plat-omap/sram.c | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index e1493d83a7c8..4f0145d26246 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c | |||
@@ -201,6 +201,15 @@ void __init omap_map_sram(void) | |||
201 | base = OMAP3_SRAM_PA; | 201 | base = OMAP3_SRAM_PA; |
202 | base = ROUND_DOWN(base, PAGE_SIZE); | 202 | base = ROUND_DOWN(base, PAGE_SIZE); |
203 | omap_sram_io_desc[0].pfn = __phys_to_pfn(base); | 203 | omap_sram_io_desc[0].pfn = __phys_to_pfn(base); |
204 | |||
205 | /* | ||
206 | * SRAM must be marked as non-cached on OMAP3 since the | ||
207 | * CORE DPLL M2 divider change code (in SRAM) runs with the | ||
208 | * SDRAM controller disabled, and if it is marked cached, | ||
209 | * the ARM may attempt to write cache lines back to SDRAM | ||
210 | * which will cause the system to hang. | ||
211 | */ | ||
212 | omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED; | ||
204 | } | 213 | } |
205 | 214 | ||
206 | omap_sram_io_desc[0].length = 1024 * 1024; /* Use section desc */ | 215 | omap_sram_io_desc[0].length = 1024 * 1024; /* Use section desc */ |
@@ -343,14 +352,15 @@ static inline int omap243x_sram_init(void) | |||
343 | static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl, | 352 | static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl, |
344 | u32 sdrc_actim_ctrla, | 353 | u32 sdrc_actim_ctrla, |
345 | u32 sdrc_actim_ctrlb, | 354 | u32 sdrc_actim_ctrlb, |
346 | u32 m2); | 355 | u32 m2, u32 unlock_dll); |
347 | u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, | 356 | u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, |
348 | u32 sdrc_actim_ctrlb, u32 m2) | 357 | u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll) |
349 | { | 358 | { |
350 | BUG_ON(!_omap3_sram_configure_core_dpll); | 359 | BUG_ON(!_omap3_sram_configure_core_dpll); |
351 | return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl, | 360 | return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl, |
352 | sdrc_actim_ctrla, | 361 | sdrc_actim_ctrla, |
353 | sdrc_actim_ctrlb, m2); | 362 | sdrc_actim_ctrlb, m2, |
363 | unlock_dll); | ||
354 | } | 364 | } |
355 | 365 | ||
356 | /* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */ | 366 | /* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */ |