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authorTony Lindgren <tony@atomide.com>2006-09-25 06:28:17 -0400
committerTony Lindgren <tony@atomide.com>2006-09-25 06:28:17 -0400
commitfb60cf4ab52f3520c2119aa42f7d4ed8e7594eb6 (patch)
treebffa8cd8f9597dc1ce330c078e1422db37e411f6 /arch/arm/plat-omap/pm.c
parent90afd5cb2ac0977c38e83b6b21493da911b242b3 (diff)
ARM: OMAP: Remove common pm.c
There is now separate pm.c for OMAP1 and OMAP2. Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/plat-omap/pm.c')
-rw-r--r--arch/arm/plat-omap/pm.c670
1 files changed, 0 insertions, 670 deletions
diff --git a/arch/arm/plat-omap/pm.c b/arch/arm/plat-omap/pm.c
deleted file mode 100644
index 04b4102727a8..000000000000
--- a/arch/arm/plat-omap/pm.c
+++ /dev/null
@@ -1,670 +0,0 @@
1/*
2 * linux/arch/arm/plat-omap/pm.c
3 *
4 * OMAP Power Management Routines
5 *
6 * Original code for the SA11x0:
7 * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
8 *
9 * Modified for the PXA250 by Nicolas Pitre:
10 * Copyright (c) 2002 Monta Vista Software, Inc.
11 *
12 * Modified for the OMAP1510 by David Singleton:
13 * Copyright (c) 2002 Monta Vista Software, Inc.
14 *
15 * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the
19 * Free Software Foundation; either version 2 of the License, or (at your
20 * option) any later version.
21 *
22 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * You should have received a copy of the GNU General Public License along
34 * with this program; if not, write to the Free Software Foundation, Inc.,
35 * 675 Mass Ave, Cambridge, MA 02139, USA.
36 */
37
38#include <linux/pm.h>
39#include <linux/sched.h>
40#include <linux/proc_fs.h>
41#include <linux/pm.h>
42#include <linux/interrupt.h>
43
44#include <asm/io.h>
45#include <asm/irq.h>
46#include <asm/mach/time.h>
47#include <asm/mach/irq.h>
48
49#include <asm/mach-types.h>
50#include <asm/arch/irqs.h>
51#include <asm/arch/tc.h>
52#include <asm/arch/pm.h>
53#include <asm/arch/mux.h>
54#include <asm/arch/tps65010.h>
55#include <asm/arch/dsp_common.h>
56
57#include <asm/arch/clock.h>
58#include <asm/arch/sram.h>
59
60static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
61static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
62static unsigned int mpui730_sleep_save[MPUI730_SLEEP_SAVE_SIZE];
63static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
64static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
65
66static void (*omap_sram_idle)(void) = NULL;
67static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
68
69/*
70 * Let's power down on idle, but only if we are really
71 * idle, because once we start down the path of
72 * going idle we continue to do idle even if we get
73 * a clock tick interrupt . .
74 */
75void omap_pm_idle(void)
76{
77 unsigned int mask32 = 0;
78
79 /*
80 * If the DSP is being used let's just idle the CPU, the overhead
81 * to wake up from Big Sleep is big, milliseconds versus micro
82 * seconds for wait for interrupt.
83 */
84
85 local_irq_disable();
86 local_fiq_disable();
87 if (need_resched()) {
88 local_fiq_enable();
89 local_irq_enable();
90 return;
91 }
92 mask32 = omap_readl(ARM_SYSST);
93
94 /*
95 * Prevent the ULPD from entering low power state by setting
96 * POWER_CTRL_REG:4 = 0
97 */
98 omap_writew(omap_readw(ULPD_POWER_CTRL) &
99 ~ULPD_DEEP_SLEEP_TRANSITION_EN, ULPD_POWER_CTRL);
100
101 /*
102 * Since an interrupt may set up a timer, we don't want to
103 * reprogram the hardware timer with interrupts enabled.
104 * Re-enable interrupts only after returning from idle.
105 */
106 timer_dyn_reprogram();
107
108 if ((mask32 & DSP_IDLE) == 0) {
109 __asm__ volatile ("mcr p15, 0, r0, c7, c0, 4");
110 } else
111 omap_sram_idle();
112
113 local_fiq_enable();
114 local_irq_enable();
115}
116
117/*
118 * Configuration of the wakeup event is board specific. For the
119 * moment we put it into this helper function. Later it may move
120 * to board specific files.
121 */
122static void omap_pm_wakeup_setup(void)
123{
124 u32 level1_wake = 0;
125 u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
126
127 /*
128 * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
129 * and the L2 wakeup interrupts: keypad and UART2. Note that the
130 * drivers must still separately call omap_set_gpio_wakeup() to
131 * wake up to a GPIO interrupt.
132 */
133 if (cpu_is_omap730())
134 level1_wake = OMAP_IRQ_BIT(INT_730_GPIO_BANK1) |
135 OMAP_IRQ_BIT(INT_730_IH2_IRQ);
136 else if (cpu_is_omap1510())
137 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
138 OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
139 else if (cpu_is_omap16xx())
140 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
141 OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
142
143 omap_writel(~level1_wake, OMAP_IH1_MIR);
144
145 if (cpu_is_omap730()) {
146 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
147 omap_writel(~(OMAP_IRQ_BIT(INT_730_WAKE_UP_REQ) | OMAP_IRQ_BIT(INT_730_MPUIO_KEYPAD)), OMAP_IH2_1_MIR);
148 } else if (cpu_is_omap1510()) {
149 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
150 omap_writel(~level2_wake, OMAP_IH2_MIR);
151 } else if (cpu_is_omap16xx()) {
152 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
153 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
154
155 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
156 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ), OMAP_IH2_1_MIR);
157 omap_writel(~0x0, OMAP_IH2_2_MIR);
158 omap_writel(~0x0, OMAP_IH2_3_MIR);
159 }
160
161 /* New IRQ agreement, recalculate in cascade order */
162 omap_writel(1, OMAP_IH2_CONTROL);
163 omap_writel(1, OMAP_IH1_CONTROL);
164}
165
166void omap_pm_suspend(void)
167{
168 unsigned long arg0 = 0, arg1 = 0;
169
170 printk("PM: OMAP%x is trying to enter deep sleep...\n", system_rev);
171
172 omap_serial_wake_trigger(1);
173
174 if (machine_is_omap_osk()) {
175 /* Stop LED1 (D9) blink */
176 tps65010_set_led(LED1, OFF);
177 }
178
179 omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
180
181 /*
182 * Step 1: turn off interrupts (FIXME: NOTE: already disabled)
183 */
184
185 local_irq_disable();
186 local_fiq_disable();
187
188 /*
189 * Step 2: save registers
190 *
191 * The omap is a strange/beautiful device. The caches, memory
192 * and register state are preserved across power saves.
193 * We have to save and restore very little register state to
194 * idle the omap.
195 *
196 * Save interrupt, MPUI, ARM and UPLD control registers.
197 */
198
199 if (cpu_is_omap730()) {
200 MPUI730_SAVE(OMAP_IH1_MIR);
201 MPUI730_SAVE(OMAP_IH2_0_MIR);
202 MPUI730_SAVE(OMAP_IH2_1_MIR);
203 MPUI730_SAVE(MPUI_CTRL);
204 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
205 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
206 MPUI730_SAVE(EMIFS_CONFIG);
207 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
208
209 } else if (cpu_is_omap1510()) {
210 MPUI1510_SAVE(OMAP_IH1_MIR);
211 MPUI1510_SAVE(OMAP_IH2_MIR);
212 MPUI1510_SAVE(MPUI_CTRL);
213 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
214 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
215 MPUI1510_SAVE(EMIFS_CONFIG);
216 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
217 } else if (cpu_is_omap16xx()) {
218 MPUI1610_SAVE(OMAP_IH1_MIR);
219 MPUI1610_SAVE(OMAP_IH2_0_MIR);
220 MPUI1610_SAVE(OMAP_IH2_1_MIR);
221 MPUI1610_SAVE(OMAP_IH2_2_MIR);
222 MPUI1610_SAVE(OMAP_IH2_3_MIR);
223 MPUI1610_SAVE(MPUI_CTRL);
224 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
225 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
226 MPUI1610_SAVE(EMIFS_CONFIG);
227 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
228 }
229
230 ARM_SAVE(ARM_CKCTL);
231 ARM_SAVE(ARM_IDLECT1);
232 ARM_SAVE(ARM_IDLECT2);
233 if (!(cpu_is_omap1510()))
234 ARM_SAVE(ARM_IDLECT3);
235 ARM_SAVE(ARM_EWUPCT);
236 ARM_SAVE(ARM_RSTCT1);
237 ARM_SAVE(ARM_RSTCT2);
238 ARM_SAVE(ARM_SYSST);
239 ULPD_SAVE(ULPD_CLOCK_CTRL);
240 ULPD_SAVE(ULPD_STATUS_REQ);
241
242 /* (Step 3 removed - we now allow deep sleep by default) */
243
244 /*
245 * Step 4: OMAP DSP Shutdown
246 */
247
248
249 /*
250 * Step 5: Wakeup Event Setup
251 */
252
253 omap_pm_wakeup_setup();
254
255 /*
256 * Step 6: ARM and Traffic controller shutdown
257 */
258
259 /* disable ARM watchdog */
260 omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
261 omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
262
263 /*
264 * Step 6b: ARM and Traffic controller shutdown
265 *
266 * Step 6 continues here. Prepare jump to power management
267 * assembly code in internal SRAM.
268 *
269 * Since the omap_cpu_suspend routine has been copied to
270 * SRAM, we'll do an indirect procedure call to it and pass the
271 * contents of arm_idlect1 and arm_idlect2 so it can restore
272 * them when it wakes up and it will return.
273 */
274
275 arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
276 arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
277
278 /*
279 * Step 6c: ARM and Traffic controller shutdown
280 *
281 * Jump to assembly code. The processor will stay there
282 * until wake up.
283 */
284 omap_sram_suspend(arg0, arg1);
285
286 /*
287 * If we are here, processor is woken up!
288 */
289
290 /*
291 * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
292 */
293
294 if (!(cpu_is_omap1510()))
295 ARM_RESTORE(ARM_IDLECT3);
296 ARM_RESTORE(ARM_CKCTL);
297 ARM_RESTORE(ARM_EWUPCT);
298 ARM_RESTORE(ARM_RSTCT1);
299 ARM_RESTORE(ARM_RSTCT2);
300 ARM_RESTORE(ARM_SYSST);
301 ULPD_RESTORE(ULPD_CLOCK_CTRL);
302 ULPD_RESTORE(ULPD_STATUS_REQ);
303
304 if (cpu_is_omap730()) {
305 MPUI730_RESTORE(EMIFS_CONFIG);
306 MPUI730_RESTORE(EMIFF_SDRAM_CONFIG);
307 MPUI730_RESTORE(OMAP_IH1_MIR);
308 MPUI730_RESTORE(OMAP_IH2_0_MIR);
309 MPUI730_RESTORE(OMAP_IH2_1_MIR);
310 } else if (cpu_is_omap1510()) {
311 MPUI1510_RESTORE(MPUI_CTRL);
312 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
313 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
314 MPUI1510_RESTORE(EMIFS_CONFIG);
315 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
316 MPUI1510_RESTORE(OMAP_IH1_MIR);
317 MPUI1510_RESTORE(OMAP_IH2_MIR);
318 } else if (cpu_is_omap16xx()) {
319 MPUI1610_RESTORE(MPUI_CTRL);
320 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
321 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
322 MPUI1610_RESTORE(EMIFS_CONFIG);
323 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
324
325 MPUI1610_RESTORE(OMAP_IH1_MIR);
326 MPUI1610_RESTORE(OMAP_IH2_0_MIR);
327 MPUI1610_RESTORE(OMAP_IH2_1_MIR);
328 MPUI1610_RESTORE(OMAP_IH2_2_MIR);
329 MPUI1610_RESTORE(OMAP_IH2_3_MIR);
330 }
331
332 omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
333
334 /*
335 * Reenable interrupts
336 */
337
338 local_irq_enable();
339 local_fiq_enable();
340
341 omap_serial_wake_trigger(0);
342
343 printk("PM: OMAP%x is re-starting from deep sleep...\n", system_rev);
344
345 if (machine_is_omap_osk()) {
346 /* Let LED1 (D9) blink again */
347 tps65010_set_led(LED1, BLINK);
348 }
349}
350
351#if defined(DEBUG) && defined(CONFIG_PROC_FS)
352static int g_read_completed;
353
354/*
355 * Read system PM registers for debugging
356 */
357static int omap_pm_read_proc(
358 char *page_buffer,
359 char **my_first_byte,
360 off_t virtual_start,
361 int length,
362 int *eof,
363 void *data)
364{
365 int my_buffer_offset = 0;
366 char * const my_base = page_buffer;
367
368 ARM_SAVE(ARM_CKCTL);
369 ARM_SAVE(ARM_IDLECT1);
370 ARM_SAVE(ARM_IDLECT2);
371 if (!(cpu_is_omap1510()))
372 ARM_SAVE(ARM_IDLECT3);
373 ARM_SAVE(ARM_EWUPCT);
374 ARM_SAVE(ARM_RSTCT1);
375 ARM_SAVE(ARM_RSTCT2);
376 ARM_SAVE(ARM_SYSST);
377
378 ULPD_SAVE(ULPD_IT_STATUS);
379 ULPD_SAVE(ULPD_CLOCK_CTRL);
380 ULPD_SAVE(ULPD_SOFT_REQ);
381 ULPD_SAVE(ULPD_STATUS_REQ);
382 ULPD_SAVE(ULPD_DPLL_CTRL);
383 ULPD_SAVE(ULPD_POWER_CTRL);
384
385 if (cpu_is_omap730()) {
386 MPUI730_SAVE(MPUI_CTRL);
387 MPUI730_SAVE(MPUI_DSP_STATUS);
388 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
389 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
390 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
391 MPUI730_SAVE(EMIFS_CONFIG);
392 } else if (cpu_is_omap1510()) {
393 MPUI1510_SAVE(MPUI_CTRL);
394 MPUI1510_SAVE(MPUI_DSP_STATUS);
395 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
396 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
397 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
398 MPUI1510_SAVE(EMIFS_CONFIG);
399 } else if (cpu_is_omap16xx()) {
400 MPUI1610_SAVE(MPUI_CTRL);
401 MPUI1610_SAVE(MPUI_DSP_STATUS);
402 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
403 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
404 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
405 MPUI1610_SAVE(EMIFS_CONFIG);
406 }
407
408 if (virtual_start == 0) {
409 g_read_completed = 0;
410
411 my_buffer_offset += sprintf(my_base + my_buffer_offset,
412 "ARM_CKCTL_REG: 0x%-8x \n"
413 "ARM_IDLECT1_REG: 0x%-8x \n"
414 "ARM_IDLECT2_REG: 0x%-8x \n"
415 "ARM_IDLECT3_REG: 0x%-8x \n"
416 "ARM_EWUPCT_REG: 0x%-8x \n"
417 "ARM_RSTCT1_REG: 0x%-8x \n"
418 "ARM_RSTCT2_REG: 0x%-8x \n"
419 "ARM_SYSST_REG: 0x%-8x \n"
420 "ULPD_IT_STATUS_REG: 0x%-4x \n"
421 "ULPD_CLOCK_CTRL_REG: 0x%-4x \n"
422 "ULPD_SOFT_REQ_REG: 0x%-4x \n"
423 "ULPD_DPLL_CTRL_REG: 0x%-4x \n"
424 "ULPD_STATUS_REQ_REG: 0x%-4x \n"
425 "ULPD_POWER_CTRL_REG: 0x%-4x \n",
426 ARM_SHOW(ARM_CKCTL),
427 ARM_SHOW(ARM_IDLECT1),
428 ARM_SHOW(ARM_IDLECT2),
429 ARM_SHOW(ARM_IDLECT3),
430 ARM_SHOW(ARM_EWUPCT),
431 ARM_SHOW(ARM_RSTCT1),
432 ARM_SHOW(ARM_RSTCT2),
433 ARM_SHOW(ARM_SYSST),
434 ULPD_SHOW(ULPD_IT_STATUS),
435 ULPD_SHOW(ULPD_CLOCK_CTRL),
436 ULPD_SHOW(ULPD_SOFT_REQ),
437 ULPD_SHOW(ULPD_DPLL_CTRL),
438 ULPD_SHOW(ULPD_STATUS_REQ),
439 ULPD_SHOW(ULPD_POWER_CTRL));
440
441 if (cpu_is_omap730()) {
442 my_buffer_offset += sprintf(my_base + my_buffer_offset,
443 "MPUI730_CTRL_REG 0x%-8x \n"
444 "MPUI730_DSP_STATUS_REG: 0x%-8x \n"
445 "MPUI730_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
446 "MPUI730_DSP_API_CONFIG_REG: 0x%-8x \n"
447 "MPUI730_SDRAM_CONFIG_REG: 0x%-8x \n"
448 "MPUI730_EMIFS_CONFIG_REG: 0x%-8x \n",
449 MPUI730_SHOW(MPUI_CTRL),
450 MPUI730_SHOW(MPUI_DSP_STATUS),
451 MPUI730_SHOW(MPUI_DSP_BOOT_CONFIG),
452 MPUI730_SHOW(MPUI_DSP_API_CONFIG),
453 MPUI730_SHOW(EMIFF_SDRAM_CONFIG),
454 MPUI730_SHOW(EMIFS_CONFIG));
455 } else if (cpu_is_omap1510()) {
456 my_buffer_offset += sprintf(my_base + my_buffer_offset,
457 "MPUI1510_CTRL_REG 0x%-8x \n"
458 "MPUI1510_DSP_STATUS_REG: 0x%-8x \n"
459 "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
460 "MPUI1510_DSP_API_CONFIG_REG: 0x%-8x \n"
461 "MPUI1510_SDRAM_CONFIG_REG: 0x%-8x \n"
462 "MPUI1510_EMIFS_CONFIG_REG: 0x%-8x \n",
463 MPUI1510_SHOW(MPUI_CTRL),
464 MPUI1510_SHOW(MPUI_DSP_STATUS),
465 MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
466 MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
467 MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
468 MPUI1510_SHOW(EMIFS_CONFIG));
469 } else if (cpu_is_omap16xx()) {
470 my_buffer_offset += sprintf(my_base + my_buffer_offset,
471 "MPUI1610_CTRL_REG 0x%-8x \n"
472 "MPUI1610_DSP_STATUS_REG: 0x%-8x \n"
473 "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
474 "MPUI1610_DSP_API_CONFIG_REG: 0x%-8x \n"
475 "MPUI1610_SDRAM_CONFIG_REG: 0x%-8x \n"
476 "MPUI1610_EMIFS_CONFIG_REG: 0x%-8x \n",
477 MPUI1610_SHOW(MPUI_CTRL),
478 MPUI1610_SHOW(MPUI_DSP_STATUS),
479 MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
480 MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
481 MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
482 MPUI1610_SHOW(EMIFS_CONFIG));
483 }
484
485 g_read_completed++;
486 } else if (g_read_completed >= 1) {
487 *eof = 1;
488 return 0;
489 }
490 g_read_completed++;
491
492 *my_first_byte = page_buffer;
493 return my_buffer_offset;
494}
495
496static void omap_pm_init_proc(void)
497{
498 struct proc_dir_entry *entry;
499
500 entry = create_proc_read_entry("driver/omap_pm",
501 S_IWUSR | S_IRUGO, NULL,
502 omap_pm_read_proc, NULL);
503}
504
505#endif /* DEBUG && CONFIG_PROC_FS */
506
507/*
508 * omap_pm_prepare - Do preliminary suspend work.
509 * @state: suspend state we're entering.
510 *
511 */
512//#include <asm/hardware.h>
513
514static int omap_pm_prepare(suspend_state_t state)
515{
516 int error = 0;
517
518 switch (state)
519 {
520 case PM_SUSPEND_STANDBY:
521 case PM_SUSPEND_MEM:
522 break;
523
524 case PM_SUSPEND_DISK:
525 return -ENOTSUPP;
526
527 default:
528 return -EINVAL;
529 }
530
531 return error;
532}
533
534
535/*
536 * omap_pm_enter - Actually enter a sleep state.
537 * @state: State we're entering.
538 *
539 */
540
541static int omap_pm_enter(suspend_state_t state)
542{
543 switch (state)
544 {
545 case PM_SUSPEND_STANDBY:
546 case PM_SUSPEND_MEM:
547 omap_pm_suspend();
548 break;
549
550 case PM_SUSPEND_DISK:
551 return -ENOTSUPP;
552
553 default:
554 return -EINVAL;
555 }
556
557 return 0;
558}
559
560
561/**
562 * omap_pm_finish - Finish up suspend sequence.
563 * @state: State we're coming out of.
564 *
565 * This is called after we wake back up (or if entering the sleep state
566 * failed).
567 */
568
569static int omap_pm_finish(suspend_state_t state)
570{
571 return 0;
572}
573
574
575static irqreturn_t omap_wakeup_interrupt(int irq, void * dev,
576 struct pt_regs * regs)
577{
578 return IRQ_HANDLED;
579}
580
581static struct irqaction omap_wakeup_irq = {
582 .name = "peripheral wakeup",
583 .flags = IRQF_DISABLED,
584 .handler = omap_wakeup_interrupt
585};
586
587
588
589static struct pm_ops omap_pm_ops ={
590 .pm_disk_mode = 0,
591 .prepare = omap_pm_prepare,
592 .enter = omap_pm_enter,
593 .finish = omap_pm_finish,
594};
595
596static int __init omap_pm_init(void)
597{
598 printk("Power Management for TI OMAP.\n");
599 /*
600 * We copy the assembler sleep/wakeup routines to SRAM.
601 * These routines need to be in SRAM as that's the only
602 * memory the MPU can see when it wakes up.
603 */
604 if (cpu_is_omap730()) {
605 omap_sram_idle = omap_sram_push(omap730_idle_loop_suspend,
606 omap730_idle_loop_suspend_sz);
607 omap_sram_suspend = omap_sram_push(omap730_cpu_suspend,
608 omap730_cpu_suspend_sz);
609 } else if (cpu_is_omap1510()) {
610 omap_sram_idle = omap_sram_push(omap1510_idle_loop_suspend,
611 omap1510_idle_loop_suspend_sz);
612 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
613 omap1510_cpu_suspend_sz);
614 } else if (cpu_is_omap16xx()) {
615 omap_sram_idle = omap_sram_push(omap1610_idle_loop_suspend,
616 omap1610_idle_loop_suspend_sz);
617 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
618 omap1610_cpu_suspend_sz);
619 }
620
621 if (omap_sram_idle == NULL || omap_sram_suspend == NULL) {
622 printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
623 return -ENODEV;
624 }
625
626 pm_idle = omap_pm_idle;
627
628 if (cpu_is_omap730())
629 setup_irq(INT_730_WAKE_UP_REQ, &omap_wakeup_irq);
630 else if (cpu_is_omap16xx())
631 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
632
633#if 0
634 /* --- BEGIN BOARD-DEPENDENT CODE --- */
635 /* Sleepx mask direction */
636 omap_writew((omap_readw(0xfffb5008) & ~2), 0xfffb5008);
637 /* Unmask sleepx signal */
638 omap_writew((omap_readw(0xfffb5004) & ~2), 0xfffb5004);
639 /* --- END BOARD-DEPENDENT CODE --- */
640#endif
641
642 /* Program new power ramp-up time
643 * (0 for most boards since we don't lower voltage when in deep sleep)
644 */
645 omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
646
647 /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
648 omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
649
650 /* Configure IDLECT3 */
651 if (cpu_is_omap730())
652 omap_writel(OMAP730_IDLECT3_VAL, OMAP730_IDLECT3);
653 else if (cpu_is_omap16xx())
654 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
655
656 pm_set_ops(&omap_pm_ops);
657
658#if defined(DEBUG) && defined(CONFIG_PROC_FS)
659 omap_pm_init_proc();
660#endif
661
662 if (cpu_is_omap16xx()) {
663 /* configure LOW_PWR pin */
664 omap_cfg_reg(T20_1610_LOW_PWR);
665 }
666
667 return 0;
668}
669__initcall(omap_pm_init);
670
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