aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/plat-omap/mux.c
diff options
context:
space:
mode:
authorTony Lindgren <tony@atomide.com>2005-07-10 14:58:18 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2005-07-10 14:58:18 -0400
commitbb13b5fdba16d5b30fe97f3d167bb138b978b71c (patch)
tree23e706d3412b29579909c499e1d9e62cc40a6f5e /arch/arm/plat-omap/mux.c
parentd48af15ea7227d633ddd5002223c2b122b1032e1 (diff)
[PATCH] ARM: 2804/1: OMAP update 9/11: Update OMAP arch files
Patch from Tony Lindgren This patch by various OMAP developers syncs the OMAP specific arch files with the linux-omap tree. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/plat-omap/mux.c')
-rw-r--r--arch/arm/plat-omap/mux.c17
1 files changed, 7 insertions, 10 deletions
diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c
index cbecd10d0b6c..ea7b955b9c81 100644
--- a/arch/arm/plat-omap/mux.c
+++ b/arch/arm/plat-omap/mux.c
@@ -53,19 +53,13 @@ omap_cfg_reg(const reg_cfg_t reg_cfg)
53 return -EINVAL; 53 return -EINVAL;
54 } 54 }
55 55
56 cfg = &reg_cfg_table[reg_cfg]; 56 cfg = (reg_cfg_set *)&reg_cfg_table[reg_cfg];
57
58 /*
59 * We do a pretty long section here with lock on, but pin muxing
60 * should only happen on driver init for each driver, so it's not time
61 * critical.
62 */
63 spin_lock_irqsave(&mux_spin_lock, flags);
64 57
65 /* Check the mux register in question */ 58 /* Check the mux register in question */
66 if (cfg->mux_reg) { 59 if (cfg->mux_reg) {
67 unsigned tmp1, tmp2; 60 unsigned tmp1, tmp2;
68 61
62 spin_lock_irqsave(&mux_spin_lock, flags);
69 reg_orig = omap_readl(cfg->mux_reg); 63 reg_orig = omap_readl(cfg->mux_reg);
70 64
71 /* The mux registers always seem to be 3 bits long */ 65 /* The mux registers always seem to be 3 bits long */
@@ -80,11 +74,13 @@ omap_cfg_reg(const reg_cfg_t reg_cfg)
80 warn = 1; 74 warn = 1;
81 75
82 omap_writel(reg, cfg->mux_reg); 76 omap_writel(reg, cfg->mux_reg);
77 spin_unlock_irqrestore(&mux_spin_lock, flags);
83 } 78 }
84 79
85 /* Check for pull up or pull down selection on 1610 */ 80 /* Check for pull up or pull down selection on 1610 */
86 if (!cpu_is_omap1510()) { 81 if (!cpu_is_omap1510()) {
87 if (cfg->pu_pd_reg && cfg->pull_val) { 82 if (cfg->pu_pd_reg && cfg->pull_val) {
83 spin_lock_irqsave(&mux_spin_lock, flags);
88 pu_pd_orig = omap_readl(cfg->pu_pd_reg); 84 pu_pd_orig = omap_readl(cfg->pu_pd_reg);
89 mask = 1 << cfg->pull_bit; 85 mask = 1 << cfg->pull_bit;
90 86
@@ -100,11 +96,13 @@ omap_cfg_reg(const reg_cfg_t reg_cfg)
100 pu_pd = pu_pd_orig & ~mask; 96 pu_pd = pu_pd_orig & ~mask;
101 } 97 }
102 omap_writel(pu_pd, cfg->pu_pd_reg); 98 omap_writel(pu_pd, cfg->pu_pd_reg);
99 spin_unlock_irqrestore(&mux_spin_lock, flags);
103 } 100 }
104 } 101 }
105 102
106 /* Check for an associated pull down register */ 103 /* Check for an associated pull down register */
107 if (cfg->pull_reg) { 104 if (cfg->pull_reg) {
105 spin_lock_irqsave(&mux_spin_lock, flags);
108 pull_orig = omap_readl(cfg->pull_reg); 106 pull_orig = omap_readl(cfg->pull_reg);
109 mask = 1 << cfg->pull_bit; 107 mask = 1 << cfg->pull_bit;
110 108
@@ -121,6 +119,7 @@ omap_cfg_reg(const reg_cfg_t reg_cfg)
121 } 119 }
122 120
123 omap_writel(pull, cfg->pull_reg); 121 omap_writel(pull, cfg->pull_reg);
122 spin_unlock_irqrestore(&mux_spin_lock, flags);
124 } 123 }
125 124
126 if (warn) { 125 if (warn) {
@@ -149,8 +148,6 @@ omap_cfg_reg(const reg_cfg_t reg_cfg)
149 } 148 }
150#endif 149#endif
151 150
152 spin_unlock_irqrestore(&mux_spin_lock, flags);
153
154#ifdef CONFIG_OMAP_MUX_ERRORS 151#ifdef CONFIG_OMAP_MUX_ERRORS
155 return warn ? -ETXTBSY : 0; 152 return warn ? -ETXTBSY : 0;
156#else 153#else