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authorJarkko Nikula <jarkko.nikula@bitmer.com>2011-09-26 03:45:41 -0400
committerTony Lindgren <tony@atomide.com>2011-09-26 20:48:01 -0400
commit88408230d2fe752ffca0f292b092642cc5c153f1 (patch)
treee9c2dfed56b19a12e981d8884b950bf253cc1c46 /arch/arm/plat-omap/mcbsp.c
parent1a6458847dd25e7ade3d633e5a374b836e38b9ae (diff)
ARM: OMAP: mcbsp: Make tranceiver configuration control register access generic
McBSP transmit and receive configuration control registers must be set up for OMAP2430 and later. Replace is_omap tests in generic code with a new feature flag has_ccr in platform data so that there is no need to change code for any upcoming OMAP version. Signed-off-by: Jarkko Nikula <jarkko.nikula@bitmer.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Tested-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/plat-omap/mcbsp.c')
-rw-r--r--arch/arm/plat-omap/mcbsp.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index 0338ad07eb71..97bcbfac068a 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -184,7 +184,7 @@ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
184 MCBSP_WRITE(mcbsp, MCR2, config->mcr2); 184 MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
185 MCBSP_WRITE(mcbsp, MCR1, config->mcr1); 185 MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
186 MCBSP_WRITE(mcbsp, PCR0, config->pcr0); 186 MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
187 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { 187 if (mcbsp->pdata->has_ccr) {
188 MCBSP_WRITE(mcbsp, XCCR, config->xccr); 188 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
189 MCBSP_WRITE(mcbsp, RCCR, config->rccr); 189 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
190 } 190 }
@@ -848,7 +848,7 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx)
848 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7)); 848 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
849 } 849 }
850 850
851 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { 851 if (mcbsp->pdata->has_ccr) {
852 /* Release the transmitter and receiver */ 852 /* Release the transmitter and receiver */
853 w = MCBSP_READ_CACHE(mcbsp, XCCR); 853 w = MCBSP_READ_CACHE(mcbsp, XCCR);
854 w &= ~(tx ? XDISABLE : 0); 854 w &= ~(tx ? XDISABLE : 0);
@@ -878,7 +878,7 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx)
878 878
879 /* Reset transmitter */ 879 /* Reset transmitter */
880 tx &= 1; 880 tx &= 1;
881 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { 881 if (mcbsp->pdata->has_ccr) {
882 w = MCBSP_READ_CACHE(mcbsp, XCCR); 882 w = MCBSP_READ_CACHE(mcbsp, XCCR);
883 w |= (tx ? XDISABLE : 0); 883 w |= (tx ? XDISABLE : 0);
884 MCBSP_WRITE(mcbsp, XCCR, w); 884 MCBSP_WRITE(mcbsp, XCCR, w);
@@ -888,7 +888,7 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx)
888 888
889 /* Reset receiver */ 889 /* Reset receiver */
890 rx &= 1; 890 rx &= 1;
891 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { 891 if (mcbsp->pdata->has_ccr) {
892 w = MCBSP_READ_CACHE(mcbsp, RCCR); 892 w = MCBSP_READ_CACHE(mcbsp, RCCR);
893 w |= (rx ? RDISABLE : 0); 893 w |= (rx ? RDISABLE : 0);
894 MCBSP_WRITE(mcbsp, RCCR, w); 894 MCBSP_WRITE(mcbsp, RCCR, w);