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authorTony Lindgren <tony@atomide.com>2012-11-02 15:24:06 -0400
committerTony Lindgren <tony@atomide.com>2012-11-20 13:04:41 -0500
commited1c7de29f9f3d56b3ca5ef69682cc1a3d369e9d (patch)
treecd61bc6adacd14f97d12e51f43171bf0b685727f /arch/arm/plat-omap/include
parentc8d35c84f5494d8d294205b598f927a11fd41f34 (diff)
ARM: OMAP2+: Move iommu2 to drivers/iommu/omap-iommu2.c
This file should not be in arch/arm. Move it to drivers/iommu to allow making most of the header local to drivers/iommu. This is needed as we are removing plat and mach includes from drivers for ARM common zImage support. Cc: Ido Yariv <ido@wizery.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: Mauro Carvalho Chehab <mchehab@infradead.org> Cc: Omar Ramirez Luna <omar.luna@linaro.org> Cc: linux-media@vger.kernel.org Acked-by: Ohad Ben-Cohen <ohad@wizery.com> Acked-by: Joerg Roedel <joro@8bytes.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/plat-omap/include')
-rw-r--r--arch/arm/plat-omap/include/plat/iommu.h272
1 files changed, 14 insertions, 258 deletions
diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
index a4b71b14975a..c677b9f2fefa 100644
--- a/arch/arm/plat-omap/include/plat/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -10,103 +10,21 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 */ 11 */
12 12
13#ifndef __MACH_IOMMU_H 13#define MMU_REG_SIZE 256
14#define __MACH_IOMMU_H
15
16#include <linux/io.h>
17
18#if defined(CONFIG_ARCH_OMAP1)
19#error "iommu for this processor not implemented yet"
20#endif
21
22struct iotlb_entry {
23 u32 da;
24 u32 pa;
25 u32 pgsz, prsvd, valid;
26 union {
27 u16 ap;
28 struct {
29 u32 endian, elsz, mixed;
30 };
31 };
32};
33
34struct omap_iommu {
35 const char *name;
36 struct module *owner;
37 struct clk *clk;
38 void __iomem *regbase;
39 struct device *dev;
40 void *isr_priv;
41 struct iommu_domain *domain;
42
43 unsigned int refcount;
44 spinlock_t iommu_lock; /* global for this whole object */
45
46 /*
47 * We don't change iopgd for a situation like pgd for a task,
48 * but share it globally for each iommu.
49 */
50 u32 *iopgd;
51 spinlock_t page_table_lock; /* protect iopgd */
52
53 int nr_tlb_entries;
54
55 struct list_head mmap;
56 struct mutex mmap_lock; /* protect mmap */
57
58 void *ctx; /* iommu context: registres saved area */
59 u32 da_start;
60 u32 da_end;
61};
62
63struct cr_regs {
64 union {
65 struct {
66 u16 cam_l;
67 u16 cam_h;
68 };
69 u32 cam;
70 };
71 union {
72 struct {
73 u16 ram_l;
74 u16 ram_h;
75 };
76 u32 ram;
77 };
78};
79
80struct iotlb_lock {
81 short base;
82 short vict;
83};
84
85/* architecture specific functions */
86struct iommu_functions {
87 unsigned long version;
88
89 int (*enable)(struct omap_iommu *obj);
90 void (*disable)(struct omap_iommu *obj);
91 void (*set_twl)(struct omap_iommu *obj, bool on);
92 u32 (*fault_isr)(struct omap_iommu *obj, u32 *ra);
93
94 void (*tlb_read_cr)(struct omap_iommu *obj, struct cr_regs *cr);
95 void (*tlb_load_cr)(struct omap_iommu *obj, struct cr_regs *cr);
96
97 struct cr_regs *(*alloc_cr)(struct omap_iommu *obj,
98 struct iotlb_entry *e);
99 int (*cr_valid)(struct cr_regs *cr);
100 u32 (*cr_to_virt)(struct cr_regs *cr);
101 void (*cr_to_e)(struct cr_regs *cr, struct iotlb_entry *e);
102 ssize_t (*dump_cr)(struct omap_iommu *obj, struct cr_regs *cr,
103 char *buf);
104
105 u32 (*get_pte_attr)(struct iotlb_entry *e);
106 14
107 void (*save_ctx)(struct omap_iommu *obj); 15/**
108 void (*restore_ctx)(struct omap_iommu *obj); 16 * struct iommu_arch_data - omap iommu private data
109 ssize_t (*dump_ctx)(struct omap_iommu *obj, char *buf, ssize_t len); 17 * @name: name of the iommu device
18 * @iommu_dev: handle of the iommu device
19 *
20 * This is an omap iommu private data object, which binds an iommu user
21 * to its iommu device. This object should be placed at the iommu user's
22 * dev_archdata so generic IOMMU API can be used without having to
23 * utilize omap-specific plumbing anymore.
24 */
25struct omap_iommu_arch_data {
26 const char *name;
27 struct omap_iommu *iommu_dev;
110}; 28};
111 29
112/** 30/**
@@ -129,165 +47,3 @@ struct iommu_platform_data {
129 u32 da_start; 47 u32 da_start;
130 u32 da_end; 48 u32 da_end;
131}; 49};
132
133/**
134 * struct iommu_arch_data - omap iommu private data
135 * @name: name of the iommu device
136 * @iommu_dev: handle of the iommu device
137 *
138 * This is an omap iommu private data object, which binds an iommu user
139 * to its iommu device. This object should be placed at the iommu user's
140 * dev_archdata so generic IOMMU API can be used without having to
141 * utilize omap-specific plumbing anymore.
142 */
143struct omap_iommu_arch_data {
144 const char *name;
145 struct omap_iommu *iommu_dev;
146};
147
148#ifdef CONFIG_IOMMU_API
149/**
150 * dev_to_omap_iommu() - retrieves an omap iommu object from a user device
151 * @dev: iommu client device
152 */
153static inline struct omap_iommu *dev_to_omap_iommu(struct device *dev)
154{
155 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
156
157 return arch_data->iommu_dev;
158}
159#endif
160
161/* IOMMU errors */
162#define OMAP_IOMMU_ERR_TLB_MISS (1 << 0)
163#define OMAP_IOMMU_ERR_TRANS_FAULT (1 << 1)
164#define OMAP_IOMMU_ERR_EMU_MISS (1 << 2)
165#define OMAP_IOMMU_ERR_TBLWALK_FAULT (1 << 3)
166#define OMAP_IOMMU_ERR_MULTIHIT_FAULT (1 << 4)
167
168/*
169 * MMU Register offsets
170 */
171#define MMU_REVISION 0x00
172#define MMU_SYSCONFIG 0x10
173#define MMU_SYSSTATUS 0x14
174#define MMU_IRQSTATUS 0x18
175#define MMU_IRQENABLE 0x1c
176#define MMU_WALKING_ST 0x40
177#define MMU_CNTL 0x44
178#define MMU_FAULT_AD 0x48
179#define MMU_TTB 0x4c
180#define MMU_LOCK 0x50
181#define MMU_LD_TLB 0x54
182#define MMU_CAM 0x58
183#define MMU_RAM 0x5c
184#define MMU_GFLUSH 0x60
185#define MMU_FLUSH_ENTRY 0x64
186#define MMU_READ_CAM 0x68
187#define MMU_READ_RAM 0x6c
188#define MMU_EMU_FAULT_AD 0x70
189
190#define MMU_REG_SIZE 256
191
192/*
193 * MMU Register bit definitions
194 */
195#define MMU_LOCK_BASE_SHIFT 10
196#define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT)
197#define MMU_LOCK_BASE(x) \
198 ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT)
199
200#define MMU_LOCK_VICT_SHIFT 4
201#define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT)
202#define MMU_LOCK_VICT(x) \
203 ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT)
204
205#define MMU_CAM_VATAG_SHIFT 12
206#define MMU_CAM_VATAG_MASK \
207 ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
208#define MMU_CAM_P (1 << 3)
209#define MMU_CAM_V (1 << 2)
210#define MMU_CAM_PGSZ_MASK 3
211#define MMU_CAM_PGSZ_1M (0 << 0)
212#define MMU_CAM_PGSZ_64K (1 << 0)
213#define MMU_CAM_PGSZ_4K (2 << 0)
214#define MMU_CAM_PGSZ_16M (3 << 0)
215
216#define MMU_RAM_PADDR_SHIFT 12
217#define MMU_RAM_PADDR_MASK \
218 ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
219
220#define MMU_RAM_ENDIAN_MASK (1 << MMU_RAM_ENDIAN_SHIFT)
221#define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT)
222
223#define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT)
224#define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT)
225#define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT)
226#define MMU_RAM_MIXED_SHIFT 6
227#define MMU_RAM_MIXED_MASK (1 << MMU_RAM_MIXED_SHIFT)
228#define MMU_RAM_MIXED MMU_RAM_MIXED_MASK
229
230/*
231 * utilities for super page(16MB, 1MB, 64KB and 4KB)
232 */
233
234#define iopgsz_max(bytes) \
235 (((bytes) >= SZ_16M) ? SZ_16M : \
236 ((bytes) >= SZ_1M) ? SZ_1M : \
237 ((bytes) >= SZ_64K) ? SZ_64K : \
238 ((bytes) >= SZ_4K) ? SZ_4K : 0)
239
240#define bytes_to_iopgsz(bytes) \
241 (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \
242 ((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \
243 ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \
244 ((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1)
245
246#define iopgsz_to_bytes(iopgsz) \
247 (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \
248 ((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \
249 ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \
250 ((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0)
251
252#define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
253
254/*
255 * global functions
256 */
257extern u32 omap_iommu_arch_version(void);
258
259extern void omap_iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e);
260
261extern int
262omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e);
263
264extern int omap_iommu_set_isr(const char *name,
265 int (*isr)(struct omap_iommu *obj, u32 da, u32 iommu_errs,
266 void *priv),
267 void *isr_priv);
268
269extern int omap_install_iommu_arch(const struct iommu_functions *ops);
270extern void omap_uninstall_iommu_arch(const struct iommu_functions *ops);
271
272extern int omap_foreach_iommu_device(void *data,
273 int (*fn)(struct device *, void *));
274
275extern ssize_t
276omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len);
277extern size_t
278omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t len);
279
280/*
281 * register accessors
282 */
283static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs)
284{
285 return __raw_readl(obj->regbase + offs);
286}
287
288static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs)
289{
290 __raw_writel(val, obj->regbase + offs);
291}
292
293#endif /* __MACH_IOMMU_H */
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