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authorTony Lindgren <tony@atomide.com>2012-10-17 14:07:18 -0400
committerTony Lindgren <tony@atomide.com>2012-10-17 14:07:18 -0400
commit99f0b8d6b09b0db6452d0d6e252bfa28049bbea9 (patch)
tree23db2359ad86957359da7c8a458e25eddb08d776 /arch/arm/plat-omap/include
parent94c657853bd228ebbc2c590b7f81efcc1dde3329 (diff)
parent94709014ea8d2f24fbc1e6eb6982e801e325bd47 (diff)
Merge branch 'omap-for-v3.8/cleanup-headers-gpmc' into omap-for-v3.8/cleanup-headers
Conflicts: arch/arm/mach-omap2/board-3430sdp.c arch/arm/mach-omap2/board-h4.c arch/arm/mach-omap2/board-rx51-peripherals.c arch/arm/mach-omap2/board-rx51.c arch/arm/mach-omap2/pm34xx.c drivers/mtd/nand/omap2.c drivers/mtd/onenand/omap2.c
Diffstat (limited to 'arch/arm/plat-omap/include')
-rw-r--r--arch/arm/plat-omap/include/plat/gpmc.h190
1 files changed, 0 insertions, 190 deletions
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
deleted file mode 100644
index 2e6e2597178c..000000000000
--- a/arch/arm/plat-omap/include/plat/gpmc.h
+++ /dev/null
@@ -1,190 +0,0 @@
1/*
2 * General-Purpose Memory Controller for OMAP2
3 *
4 * Copyright (C) 2005-2006 Nokia Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __OMAP2_GPMC_H
12#define __OMAP2_GPMC_H
13
14/* Maximum Number of Chip Selects */
15#define GPMC_CS_NUM 8
16
17#define GPMC_CS_CONFIG1 0x00
18#define GPMC_CS_CONFIG2 0x04
19#define GPMC_CS_CONFIG3 0x08
20#define GPMC_CS_CONFIG4 0x0c
21#define GPMC_CS_CONFIG5 0x10
22#define GPMC_CS_CONFIG6 0x14
23#define GPMC_CS_CONFIG7 0x18
24#define GPMC_CS_NAND_COMMAND 0x1c
25#define GPMC_CS_NAND_ADDRESS 0x20
26#define GPMC_CS_NAND_DATA 0x24
27
28/* Control Commands */
29#define GPMC_CONFIG_RDY_BSY 0x00000001
30#define GPMC_CONFIG_DEV_SIZE 0x00000002
31#define GPMC_CONFIG_DEV_TYPE 0x00000003
32#define GPMC_SET_IRQ_STATUS 0x00000004
33#define GPMC_CONFIG_WP 0x00000005
34
35#define GPMC_GET_IRQ_STATUS 0x00000006
36#define GPMC_PREFETCH_FIFO_CNT 0x00000007 /* bytes available in FIFO for r/w */
37#define GPMC_PREFETCH_COUNT 0x00000008 /* remaining bytes to be read/write*/
38#define GPMC_STATUS_BUFFER 0x00000009 /* 1: buffer is available to write */
39
40#define GPMC_NAND_COMMAND 0x0000000a
41#define GPMC_NAND_ADDRESS 0x0000000b
42#define GPMC_NAND_DATA 0x0000000c
43
44#define GPMC_ENABLE_IRQ 0x0000000d
45
46/* ECC commands */
47#define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
48#define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
49#define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
50
51#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
52#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
53#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
54#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
55#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
56#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
57#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
58#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
59#define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
60#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
61#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
62#define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
63#define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
64#define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
65#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
66#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
67#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
68#define GPMC_CONFIG1_MUXADDDATA (1 << 9)
69#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
70#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
71#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
72#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
73#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
74#define GPMC_CONFIG7_CSVALID (1 << 6)
75
76#define GPMC_DEVICETYPE_NOR 0
77#define GPMC_DEVICETYPE_NAND 2
78#define GPMC_CONFIG_WRITEPROTECT 0x00000010
79#define GPMC_STATUS_BUFF_EMPTY 0x00000001
80#define WR_RD_PIN_MONITORING 0x00600000
81#define GPMC_PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
82#define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
83#define GPMC_IRQ_FIFOEVENTENABLE 0x01
84#define GPMC_IRQ_COUNT_EVENT 0x02
85
86#define PREFETCH_FIFOTHRESHOLD_MAX 0x40
87#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
88
89enum omap_ecc {
90 /* 1-bit ecc: stored at end of spare area */
91 OMAP_ECC_HAMMING_CODE_DEFAULT = 0, /* Default, s/w method */
92 OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */
93 /* 1-bit ecc: stored at beginning of spare area as romcode */
94 OMAP_ECC_HAMMING_CODE_HW_ROMCODE, /* gpmc method & romcode layout */
95 OMAP_ECC_BCH4_CODE_HW, /* 4-bit BCH ecc code */
96 OMAP_ECC_BCH8_CODE_HW, /* 8-bit BCH ecc code */
97};
98
99/*
100 * Note that all values in this struct are in nanoseconds except sync_clk
101 * (which is in picoseconds), while the register values are in gpmc_fck cycles.
102 */
103struct gpmc_timings {
104 /* Minimum clock period for synchronous mode (in picoseconds) */
105 u32 sync_clk;
106
107 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
108 u16 cs_on; /* Assertion time */
109 u16 cs_rd_off; /* Read deassertion time */
110 u16 cs_wr_off; /* Write deassertion time */
111
112 /* ADV signal timings corresponding to GPMC_CONFIG3 */
113 u16 adv_on; /* Assertion time */
114 u16 adv_rd_off; /* Read deassertion time */
115 u16 adv_wr_off; /* Write deassertion time */
116
117 /* WE signals timings corresponding to GPMC_CONFIG4 */
118 u16 we_on; /* WE assertion time */
119 u16 we_off; /* WE deassertion time */
120
121 /* OE signals timings corresponding to GPMC_CONFIG4 */
122 u16 oe_on; /* OE assertion time */
123 u16 oe_off; /* OE deassertion time */
124
125 /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
126 u16 page_burst_access; /* Multiple access word delay */
127 u16 access; /* Start-cycle to first data valid delay */
128 u16 rd_cycle; /* Total read cycle time */
129 u16 wr_cycle; /* Total write cycle time */
130
131 /* The following are only on OMAP3430 */
132 u16 wr_access; /* WRACCESSTIME */
133 u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */
134};
135
136struct gpmc_nand_regs {
137 void __iomem *gpmc_status;
138 void __iomem *gpmc_nand_command;
139 void __iomem *gpmc_nand_address;
140 void __iomem *gpmc_nand_data;
141 void __iomem *gpmc_prefetch_config1;
142 void __iomem *gpmc_prefetch_config2;
143 void __iomem *gpmc_prefetch_control;
144 void __iomem *gpmc_prefetch_status;
145 void __iomem *gpmc_ecc_config;
146 void __iomem *gpmc_ecc_control;
147 void __iomem *gpmc_ecc_size_config;
148 void __iomem *gpmc_ecc1_result;
149 void __iomem *gpmc_bch_result0;
150};
151
152extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
153extern int gpmc_get_client_irq(unsigned irq_config);
154
155extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
156extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps);
157extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
158extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
159extern unsigned long gpmc_get_fclk_period(void);
160
161extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
162extern u32 gpmc_cs_read_reg(int cs, int idx);
163extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk);
164extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
165extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
166extern void gpmc_cs_free(int cs);
167extern int gpmc_cs_set_reserved(int cs, int reserved);
168extern int gpmc_cs_reserved(int cs);
169extern int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
170 unsigned int u32_count, int is_write);
171extern int gpmc_prefetch_reset(int cs);
172extern void omap3_gpmc_save_context(void);
173extern void omap3_gpmc_restore_context(void);
174extern int gpmc_read_status(int cmd);
175extern int gpmc_cs_configure(int cs, int cmd, int wval);
176extern int gpmc_nand_read(int cs, int cmd);
177extern int gpmc_nand_write(int cs, int cmd, int wval);
178
179int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size);
180int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code);
181
182#ifdef CONFIG_ARCH_OMAP3
183int gpmc_init_hwecc_bch(int cs, int nsectors, int nerrors);
184int gpmc_enable_hwecc_bch(int cs, int mode, int dev_width, int nsectors,
185 int nerrors);
186int gpmc_calculate_ecc_bch4(int cs, const u_char *dat, u_char *ecc);
187int gpmc_calculate_ecc_bch8(int cs, const u_char *dat, u_char *ecc);
188#endif /* CONFIG_ARCH_OMAP3 */
189
190#endif
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