Merge branch 'omap/dt' into next/dt

9 files changed, 292 insertions, 332 deletions

diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index df4b9683f17f..197ca03c3f7d 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -80,8 +80,6 @@ struct clkops {
  *
  * @div is the divisor that should be applied to the parent clock's rate
  * to produce the current clock's rate.
- *
- * XXX @flags probably should be replaced with an struct omap_chip.
  */
 struct clksel_rate {
         u32                     val;
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index 4564cc697d7f..abda2c7e499b 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -45,6 +45,15 @@ extern unsigned long long notrace omap_32k_sched_clock(void);
 
 extern void omap_reserve(void);
 
+void omap2420_init_early(void);
+void omap2430_init_early(void);
+void omap3430_init_early(void);
+void omap35xx_init_early(void);
+void omap3630_init_early(void);
+void am35xx_init_early(void);
+void ti816x_init_early(void);
+void omap4430_init_early(void);
+
 /*
  * IO bases for various OMAP processors
  * Except the tap base, rest all the io bases
@@ -74,7 +83,11 @@ void omap2_set_globals_sdrc(struct omap_globals *);
 void omap2_set_globals_control(struct omap_globals *);
 void omap2_set_globals_prcm(struct omap_globals *);
 
+void omap242x_map_io(void);
+void omap243x_map_io(void);
 void omap3_map_io(void);
+void omap4_map_io(void);
+
 
 /**
  * omap_test_timeout - busy-loop, testing a condition
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 67b3d75884cd..2f9026942229 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -44,13 +44,6 @@
 
 int omap_type(void);
 
-struct omap_chip_id {
-        u16 oc;
-        u8 type;
-};
-
-#define OMAP_CHIP_INIT(x)       { .oc = x }
-
 /*
  * omap_rev bits:
  * CPU id bits  (0730, 1510, 1710, 2422...)     [31:16]
@@ -60,19 +53,6 @@ struct omap_chip_id {
 unsigned int omap_rev(void);
 
 /*
- * Define CPU revision bits
- *
- * Verbose meaning of the revision bits may be different for a silicon
- * family. This difference can be handled separately.
- */
-#define OMAP_REVBITS_00         0x00
-#define OMAP_REVBITS_01         0x01
-#define OMAP_REVBITS_02         0x02
-#define OMAP_REVBITS_03         0x03
-#define OMAP_REVBITS_04         0x04
-#define OMAP_REVBITS_05         0x05
-
-/*
  * Get the CPU revision for OMAP devices
  */
 #define GET_OMAP_REVISION()     ((omap_rev() >> 8) & 0xff)
@@ -262,7 +242,7 @@ IS_OMAP_TYPE(2422, 0x2422)
 IS_OMAP_TYPE(2423, 0x2423)
 IS_OMAP_TYPE(2430, 0x2430)
 IS_OMAP_TYPE(3430, 0x3430)
-IS_OMAP_TYPE(3505, 0x3505)
+IS_OMAP_TYPE(3505, 0x3517)
 IS_OMAP_TYPE(3517, 0x3517)
 
 #define cpu_is_omap310()                0
@@ -354,8 +334,9 @@ IS_OMAP_TYPE(3517, 0x3517)
                                                 (!omap3_has_sgx()) &&   \
                                                 (omap3_has_iva()))
 # define cpu_is_omap3530()              (cpu_is_omap3430())
-# define cpu_is_omap3505()              is_omap3505()
 # define cpu_is_omap3517()              is_omap3517()
+# define cpu_is_omap3505()              (cpu_is_omap3517() &&           \
+                                                !omap3_has_sgx())
 # undef cpu_is_omap3630
 # define cpu_is_omap3630()              is_omap363x()
 # define cpu_is_ti816x()                is_ti816x()
@@ -379,35 +360,31 @@ IS_OMAP_TYPE(3517, 0x3517)
 /* Various silicon revisions for omap2 */
 #define OMAP242X_CLASS          0x24200024
 #define OMAP2420_REV_ES1_0      OMAP242X_CLASS
-#define OMAP2420_REV_ES2_0      (OMAP242X_CLASS | (OMAP_REVBITS_01 << 8))
+#define OMAP2420_REV_ES2_0      (OMAP242X_CLASS | (0x1 << 8))
 
 #define OMAP243X_CLASS          0x24300024
 #define OMAP2430_REV_ES1_0      OMAP243X_CLASS
 
 #define OMAP343X_CLASS          0x34300034
 #define OMAP3430_REV_ES1_0      OMAP343X_CLASS
-#define OMAP3430_REV_ES2_0      (OMAP343X_CLASS | (OMAP_REVBITS_01 << 8))
-#define OMAP3430_REV_ES2_1      (OMAP343X_CLASS | (OMAP_REVBITS_02 << 8))
-#define OMAP3430_REV_ES3_0      (OMAP343X_CLASS | (OMAP_REVBITS_03 << 8))
-#define OMAP3430_REV_ES3_1      (OMAP343X_CLASS | (OMAP_REVBITS_04 << 8))
-#define OMAP3430_REV_ES3_1_2    (OMAP343X_CLASS | (OMAP_REVBITS_05 << 8))
+#define OMAP3430_REV_ES2_0      (OMAP343X_CLASS | (0x1 << 8))
+#define OMAP3430_REV_ES2_1      (OMAP343X_CLASS | (0x2 << 8))
+#define OMAP3430_REV_ES3_0      (OMAP343X_CLASS | (0x3 << 8))
+#define OMAP3430_REV_ES3_1      (OMAP343X_CLASS | (0x4 << 8))
+#define OMAP3430_REV_ES3_1_2    (OMAP343X_CLASS | (0x5 << 8))
 
 #define OMAP363X_CLASS          0x36300034
 #define OMAP3630_REV_ES1_0      OMAP363X_CLASS
-#define OMAP3630_REV_ES1_1      (OMAP363X_CLASS | (OMAP_REVBITS_01 << 8))
-#define OMAP3630_REV_ES1_2      (OMAP363X_CLASS | (OMAP_REVBITS_02 << 8))
+#define OMAP3630_REV_ES1_1      (OMAP363X_CLASS | (0x1 << 8))
+#define OMAP3630_REV_ES1_2      (OMAP363X_CLASS | (0x2 << 8))
 
-#define OMAP35XX_CLASS          0x35000034
-#define OMAP3503_REV(v)         (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8))
-#define OMAP3515_REV(v)         (OMAP35XX_CLASS | (0x3515 << 16) | (v << 8))
-#define OMAP3525_REV(v)         (OMAP35XX_CLASS | (0x3525 << 16) | (v << 8))
-#define OMAP3530_REV(v)         (OMAP35XX_CLASS | (0x3530 << 16) | (v << 8))
-#define OMAP3505_REV(v)         (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8))
-#define OMAP3517_REV(v)         (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8))
+#define OMAP3517_CLASS          0x35170034
+#define OMAP3517_REV_ES1_0      OMAP3517_CLASS
+#define OMAP3517_REV_ES1_1      (OMAP3517_CLASS | (0x1 << 8))
 
 #define TI816X_CLASS            0x81600034
 #define TI8168_REV_ES1_0        TI816X_CLASS
-#define TI8168_REV_ES1_1        (TI816X_CLASS | (OMAP_REVBITS_01 << 8))
+#define TI8168_REV_ES1_1        (TI816X_CLASS | (0x1 << 8))
 
 #define OMAP443X_CLASS          0x44300044
 #define OMAP4430_REV_ES1_0      (OMAP443X_CLASS | (0x10 << 8))
@@ -418,61 +395,6 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define OMAP446X_CLASS          0x44600044
 #define OMAP4460_REV_ES1_0      (OMAP446X_CLASS | (0x10 << 8))
 
-/*
- * omap_chip bits
- *
- * CHIP_IS_OMAP{2420,2430,3430} indicate that a particular structure is
- * valid on all chips of that type.  CHIP_IS_OMAP3430ES{1,2} indicates
- * something that is only valid on that particular ES revision.
- *
- * These bits may be ORed together to indicate structures that are
- * available on multiple chip types.
- *
- * To test whether a particular structure matches the current OMAP chip type,
- * use omap_chip_is().
- *
- */
-#define CHIP_IS_OMAP2420                (1 << 0)
-#define CHIP_IS_OMAP2430                (1 << 1)
-#define CHIP_IS_OMAP3430                (1 << 2)
-#define CHIP_IS_OMAP3430ES1             (1 << 3)
-#define CHIP_IS_OMAP3430ES2             (1 << 4)
-#define CHIP_IS_OMAP3430ES3_0           (1 << 5)
-#define CHIP_IS_OMAP3430ES3_1           (1 << 6)
-#define CHIP_IS_OMAP3630ES1             (1 << 7)
-#define CHIP_IS_OMAP4430ES1             (1 << 8)
-#define CHIP_IS_OMAP3630ES1_1           (1 << 9)
-#define CHIP_IS_OMAP3630ES1_2           (1 << 10)
-#define CHIP_IS_OMAP4430ES2             (1 << 11)
-#define CHIP_IS_OMAP4430ES2_1           (1 << 12)
-#define CHIP_IS_OMAP4430ES2_2           (1 << 13)
-#define CHIP_IS_TI816X                  (1 << 14)
-#define CHIP_IS_OMAP4460ES1_0           (1 << 15)
-
-#define CHIP_IS_OMAP24XX                (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
-
-#define CHIP_IS_OMAP4430                (CHIP_IS_OMAP4430ES1 |          \
-                                         CHIP_IS_OMAP4430ES2 |          \
-                                         CHIP_IS_OMAP4430ES2_1 |        \
-                                         CHIP_IS_OMAP4430ES2_2 |        \
-                                         CHIP_IS_OMAP4460ES1_0)
-
-/*
- * "GE" here represents "greater than or equal to" in terms of ES
- * levels.  So CHIP_GE_OMAP3430ES2 is intended to match all OMAP3430
- * chips at ES2 and beyond, but not, for example, any OMAP lines after
- * OMAP3.
- */
-#define CHIP_GE_OMAP3430ES2             (CHIP_IS_OMAP3430ES2 | \
-                                         CHIP_IS_OMAP3430ES3_0 | \
-                                         CHIP_GE_OMAP3430ES3_1)
-#define CHIP_GE_OMAP3430ES3_1           (CHIP_IS_OMAP3430ES3_1 | \
-                                         CHIP_IS_OMAP3630ES1 | \
-                                         CHIP_GE_OMAP3630ES1_1)
-#define CHIP_GE_OMAP3630ES1_1           (CHIP_IS_OMAP3630ES1_1 | \
-                                         CHIP_IS_OMAP3630ES1_2)
-
-int omap_chip_is(struct omap_chip_id oci);
 void omap2_check_revision(void);
 
 /*
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index eb5d16c60cd9..d11025e6e7a4 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -1,5 +1,5 @@
 /*
- * arch/arm/plat-omap/include/mach/dmtimer.h
+ * arch/arm/plat-omap/include/plat/dmtimer.h
  *
  * OMAP Dual-Mode Timers
  *
@@ -35,6 +35,7 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/io.h>
+#include <linux/platform_device.h>
 
 #ifndef __ASM_ARCH_DMTIMER_H
 #define __ASM_ARCH_DMTIMER_H
@@ -59,12 +60,56 @@
  * in OMAP4 can be distinguished.
  */
 #define OMAP_TIMER_IP_VERSION_1                        0x1
+
+/* timer capabilities used in hwmod database */
+#define OMAP_TIMER_SECURE                               0x80000000
+#define OMAP_TIMER_ALWON                                0x40000000
+#define OMAP_TIMER_HAS_PWM                              0x20000000
+
+struct omap_timer_capability_dev_attr {
+        u32 timer_capability;
+};
+
 struct omap_dm_timer;
 struct clk;
 
+struct timer_regs {
+        u32 tidr;
+        u32 tiocp_cfg;
+        u32 tistat;
+        u32 tisr;
+        u32 tier;
+        u32 twer;
+        u32 tclr;
+        u32 tcrr;
+        u32 tldr;
+        u32 ttrg;
+        u32 twps;
+        u32 tmar;
+        u32 tcar1;
+        u32 tsicr;
+        u32 tcar2;
+        u32 tpir;
+        u32 tnir;
+        u32 tcvr;
+        u32 tocr;
+        u32 towr;
+};
+
+struct dmtimer_platform_data {
+        int (*set_timer_src)(struct platform_device *pdev, int source);
+        int timer_ip_version;
+        u32 needs_manual_reset:1;
+        bool reserved;
+
+        bool loses_context;
+
+        u32 (*get_context_loss_count)(struct device *dev);
+};
+
 struct omap_dm_timer *omap_dm_timer_request(void);
 struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
-void omap_dm_timer_free(struct omap_dm_timer *timer);
+int omap_dm_timer_free(struct omap_dm_timer *timer);
 void omap_dm_timer_enable(struct omap_dm_timer *timer);
 void omap_dm_timer_disable(struct omap_dm_timer *timer);
 
@@ -73,23 +118,23 @@ int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
 u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
 
-void omap_dm_timer_trigger(struct omap_dm_timer *timer);
-void omap_dm_timer_start(struct omap_dm_timer *timer);
-void omap_dm_timer_stop(struct omap_dm_timer *timer);
+int omap_dm_timer_trigger(struct omap_dm_timer *timer);
+int omap_dm_timer_start(struct omap_dm_timer *timer);
+int omap_dm_timer_stop(struct omap_dm_timer *timer);
 
 int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
-void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
-void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
-void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
-void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
-void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
+int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
+int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
+int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
+int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
+int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
 
-void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
+int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
 
 unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
-void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
+int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
 unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
-void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
+int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
 
 int omap_dm_timers_active(void);
 
@@ -98,12 +143,30 @@ int omap_dm_timers_active(void);
  * used by dmtimer.c and sys_timer related code.
  */
 
-/* register offsets */
-#define _OMAP_TIMER_ID_OFFSET           0x00
-#define _OMAP_TIMER_OCP_CFG_OFFSET      0x10
-#define _OMAP_TIMER_SYS_STAT_OFFSET     0x14
-#define _OMAP_TIMER_STAT_OFFSET         0x18
-#define _OMAP_TIMER_INT_EN_OFFSET       0x1c
+/*
+ * The interrupt registers are different between v1 and v2 ip.
+ * These registers are offsets from timer->iobase.
+ */
+#define OMAP_TIMER_ID_OFFSET            0x00
+#define OMAP_TIMER_OCP_CFG_OFFSET       0x10
+
+#define OMAP_TIMER_V1_SYS_STAT_OFFSET   0x14
+#define OMAP_TIMER_V1_STAT_OFFSET       0x18
+#define OMAP_TIMER_V1_INT_EN_OFFSET     0x1c
+
+#define OMAP_TIMER_V2_IRQSTATUS_RAW     0x24
+#define OMAP_TIMER_V2_IRQSTATUS         0x28
+#define OMAP_TIMER_V2_IRQENABLE_SET     0x2c
+#define OMAP_TIMER_V2_IRQENABLE_CLR     0x30
+
+/*
+ * The functional registers have a different base on v1 and v2 ip.
+ * These registers are offsets from timer->func_base. The func_base
+ * is samae as io_base for v1 and io_base + 0x14 for v2 ip.
+ *
+ */
+#define OMAP_TIMER_V2_FUNC_OFFSET               0x14
+
 #define _OMAP_TIMER_WAKEUP_EN_OFFSET    0x20
 #define _OMAP_TIMER_CTRL_OFFSET         0x24
 #define         OMAP_TIMER_CTRL_GPOCFG          (1 << 14)
@@ -147,21 +210,6 @@ int omap_dm_timers_active(void);
 /* register offsets with the write pending bit encoded */
 #define WPSHIFT                                 16
 
-#define OMAP_TIMER_ID_REG                       (_OMAP_TIMER_ID_OFFSET \
-                                                        | (WP_NONE << WPSHIFT))
-
-#define OMAP_TIMER_OCP_CFG_REG                  (_OMAP_TIMER_OCP_CFG_OFFSET \
-                                                        | (WP_NONE << WPSHIFT))
-
-#define OMAP_TIMER_SYS_STAT_REG                 (_OMAP_TIMER_SYS_STAT_OFFSET \
-                                                        | (WP_NONE << WPSHIFT))
-
-#define OMAP_TIMER_STAT_REG                     (_OMAP_TIMER_STAT_OFFSET \
-                                                        | (WP_NONE << WPSHIFT))
-
-#define OMAP_TIMER_INT_EN_REG                   (_OMAP_TIMER_INT_EN_OFFSET \
-                                                        | (WP_NONE << WPSHIFT))
-
 #define OMAP_TIMER_WAKEUP_EN_REG                (_OMAP_TIMER_WAKEUP_EN_OFFSET \
                                                         | (WP_NONE << WPSHIFT))
 
@@ -209,49 +257,88 @@ int omap_dm_timers_active(void);
 
 struct omap_dm_timer {
         unsigned long phys_base;
+        int id;
         int irq;
-#ifdef CONFIG_ARCH_OMAP2PLUS
         struct clk *iclk, *fclk;
-#endif
-        void __iomem *io_base;
+
+        void __iomem    *io_base;
+        void __iomem    *sys_stat;      /* TISTAT timer status */
+        void __iomem    *irq_stat;      /* TISR/IRQSTATUS interrupt status */
+        void __iomem    *irq_ena;       /* irq enable */
+        void __iomem    *irq_dis;       /* irq disable, only on v2 ip */
+        void __iomem    *pend;          /* write pending */
+        void __iomem    *func_base;     /* function register base */
+
         unsigned long rate;
         unsigned reserved:1;
-        unsigned enabled:1;
         unsigned posted:1;
+        struct timer_regs context;
+        bool loses_context;
+        int ctx_loss_count;
+        int revision;
+        struct platform_device *pdev;
+        struct list_head node;
+
+        u32 (*get_context_loss_count)(struct device *dev);
 };
 
-extern u32 sys_timer_reserved;
-void omap_dm_timer_prepare(struct omap_dm_timer *timer);
+int omap_dm_timer_prepare(struct omap_dm_timer *timer);
 
-static inline u32 __omap_dm_timer_read(void __iomem *base, u32 reg,
+static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg,
                                                 int posted)
 {
         if (posted)
-                while (__raw_readl(base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
-                                & (reg >> WPSHIFT))
+                while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
                         cpu_relax();
 
-        return __raw_readl(base + (reg & 0xff));
+        return __raw_readl(timer->func_base + (reg & 0xff));
 }
 
-static inline void __omap_dm_timer_write(void __iomem *base, u32 reg, u32 val,
-                                                int posted)
+static inline void __omap_dm_timer_write(struct omap_dm_timer *timer,
+                                        u32 reg, u32 val, int posted)
 {
         if (posted)
-                while (__raw_readl(base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
-                                & (reg >> WPSHIFT))
+                while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
                         cpu_relax();
 
-        __raw_writel(val, base + (reg & 0xff));
+        __raw_writel(val, timer->func_base + (reg & 0xff));
+}
+
+static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
+{
+        u32 tidr;
+
+        /* Assume v1 ip if bits [31:16] are zero */
+        tidr = __raw_readl(timer->io_base);
+        if (!(tidr >> 16)) {
+                timer->revision = 1;
+                timer->sys_stat = timer->io_base +
+                                OMAP_TIMER_V1_SYS_STAT_OFFSET;
+                timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
+                timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
+                timer->irq_dis = 0;
+                timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
+                timer->func_base = timer->io_base;
+        } else {
+                timer->revision = 2;
+                timer->sys_stat = 0;
+                timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS;
+                timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;
+                timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR;
+                timer->pend = timer->io_base +
+                        _OMAP_TIMER_WRITE_PEND_OFFSET +
+                                OMAP_TIMER_V2_FUNC_OFFSET;
+                timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET;
+        }
 }
 
 /* Assumes the source clock has been set by caller */
-static inline void __omap_dm_timer_reset(void __iomem *base, int autoidle,
-                                                int wakeup)
+static inline void __omap_dm_timer_reset(struct omap_dm_timer *timer,
+                                        int autoidle, int wakeup)
 {
         u32 l;
 
-        l = __omap_dm_timer_read(base, OMAP_TIMER_OCP_CFG_REG, 0);
+        l = __raw_readl(timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
         l |= 0x02 << 3;  /* Set to smart-idle mode */
         l |= 0x2 << 8;   /* Set clock activity to perserve f-clock on idle */
 
@@ -261,10 +348,10 @@ static inline void __omap_dm_timer_reset(void __iomem *base, int autoidle,
         if (wakeup)
                 l |= 1 << 2;
 
-        __omap_dm_timer_write(base, OMAP_TIMER_OCP_CFG_REG, l, 0);
+        __raw_writel(l, timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
 
         /* Match hardware reset default of posted mode */
-        __omap_dm_timer_write(base, OMAP_TIMER_IF_CTRL_REG,
+        __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
                                         OMAP_TIMER_CTRL_POSTED, 0);
 }
 
@@ -286,18 +373,18 @@ static inline int __omap_dm_timer_set_source(struct clk *timer_fck,
         return ret;
 }
 
-static inline void __omap_dm_timer_stop(void __iomem *base, int posted,
-                                                unsigned long rate)
+static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer,
+                                        int posted, unsigned long rate)
 {
         u32 l;
 
-        l = __omap_dm_timer_read(base, OMAP_TIMER_CTRL_REG, posted);
+        l = __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
         if (l & OMAP_TIMER_CTRL_ST) {
                 l &= ~0x1;
-                __omap_dm_timer_write(base, OMAP_TIMER_CTRL_REG, l, posted);
+                __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, l, posted);
 #ifdef CONFIG_ARCH_OMAP2PLUS
                 /* Readback to make sure write has completed */
-                __omap_dm_timer_read(base, OMAP_TIMER_CTRL_REG, posted);
+                __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
                 /*
                  * Wait for functional clock period x 3.5 to make sure that
                  * timer is stopped
@@ -307,34 +394,34 @@ static inline void __omap_dm_timer_stop(void __iomem *base, int posted,
         }
 
         /* Ack possibly pending interrupt */
-        __omap_dm_timer_write(base, OMAP_TIMER_STAT_REG,
-                                        OMAP_TIMER_INT_OVERFLOW, 0);
+        __raw_writel(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat);
 }
 
-static inline void __omap_dm_timer_load_start(void __iomem *base, u32 ctrl,
-                                                unsigned int load, int posted)
+static inline void __omap_dm_timer_load_start(struct omap_dm_timer *timer,
+                                                u32 ctrl, unsigned int load,
+                                                int posted)
 {
-        __omap_dm_timer_write(base, OMAP_TIMER_COUNTER_REG, load, posted);
-        __omap_dm_timer_write(base, OMAP_TIMER_CTRL_REG, ctrl, posted);
+        __omap_dm_timer_write(timer, OMAP_TIMER_COUNTER_REG, load, posted);
+        __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, ctrl, posted);
 }
 
-static inline void __omap_dm_timer_int_enable(void __iomem *base,
+static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer,
                                                 unsigned int value)
 {
-        __omap_dm_timer_write(base, OMAP_TIMER_INT_EN_REG, value, 0);
-        __omap_dm_timer_write(base, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
+        __raw_writel(value, timer->irq_ena);
+        __omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
 }
 
-static inline unsigned int __omap_dm_timer_read_counter(void __iomem *base,
-                                                        int posted)
+static inline unsigned int
+__omap_dm_timer_read_counter(struct omap_dm_timer *timer, int posted)
 {
-        return __omap_dm_timer_read(base, OMAP_TIMER_COUNTER_REG, posted);
+        return __omap_dm_timer_read(timer, OMAP_TIMER_COUNTER_REG, posted);
 }
 
-static inline void __omap_dm_timer_write_status(void __iomem *base,
+static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer,
                                                 unsigned int value)
 {
-        __omap_dm_timer_write(base, OMAP_TIMER_STAT_REG, value, 0);
+        __raw_writel(value, timer->irq_stat);
 }
 
 #endif /* __ASM_ARCH_DMTIMER_H */
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
index d72ec85c97e6..6591875486d5 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -228,13 +228,13 @@
 
 #define OMAP44XX_EMIF2_PHYS     OMAP44XX_EMIF2_BASE
                                                 /* 0x4d000000 --> 0xfd200000 */
-#define OMAP44XX_EMIF2_VIRT     (OMAP44XX_EMIF2_PHYS + OMAP4_L3_PER_IO_OFFSET)
 #define OMAP44XX_EMIF2_SIZE     SZ_1M
+#define OMAP44XX_EMIF2_VIRT     (OMAP44XX_EMIF1_VIRT + OMAP44XX_EMIF1_SIZE)
 
 #define OMAP44XX_DMM_PHYS       OMAP44XX_DMM_BASE
                                                 /* 0x4e000000 --> 0xfd300000 */
-#define OMAP44XX_DMM_VIRT       (OMAP44XX_DMM_PHYS + OMAP4_L3_PER_IO_OFFSET)
 #define OMAP44XX_DMM_SIZE       SZ_1M
+#define OMAP44XX_DMM_VIRT       (OMAP44XX_EMIF2_VIRT + OMAP44XX_EMIF2_SIZE)
 /*
  * ----------------------------------------------------------------------------
  * Omap specific register access
@@ -300,7 +300,7 @@ static inline void omap44xx_map_common_io(void)
 #endif
 
 extern void omap2_init_common_infrastructure(void);
-extern void omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
+extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
                                       struct omap_sdrc_params *sdrc_cs1);
 
 #define __arch_ioremap  omap_ioremap
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index 9882c657b2d4..8fa74e2c9d6e 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -25,9 +25,7 @@
 #define __ASM_ARCH_OMAP_MCBSP_H
 
 #include <linux/spinlock.h>
-
-#include <mach/hardware.h>
-#include <plat/clock.h>
+#include <linux/clk.h>
 
 /* macro for building platform_device for McBSP ports */
 #define OMAP_MCBSP_PLATFORM_DEVICE(port_nr)             \
@@ -40,104 +38,60 @@ static struct platform_device omap_mcbsp##port_nr = {	\
 #define MCBSP_CONFIG_TYPE3      0x3
 #define MCBSP_CONFIG_TYPE4      0x4
 
-#define OMAP7XX_MCBSP1_BASE     0xfffb1000
-#define OMAP7XX_MCBSP2_BASE     0xfffb1800
-
-#define OMAP1510_MCBSP1_BASE    0xe1011800
-#define OMAP1510_MCBSP2_BASE    0xfffb1000
-#define OMAP1510_MCBSP3_BASE    0xe1017000
-
-#define OMAP1610_MCBSP1_BASE    0xe1011800
-#define OMAP1610_MCBSP2_BASE    0xfffb1000
-#define OMAP1610_MCBSP3_BASE    0xe1017000
-
-#ifdef CONFIG_ARCH_OMAP1
-
-#define OMAP_MCBSP_REG_DRR2     0x00
-#define OMAP_MCBSP_REG_DRR1     0x02
-#define OMAP_MCBSP_REG_DXR2     0x04
-#define OMAP_MCBSP_REG_DXR1     0x06
-#define OMAP_MCBSP_REG_DRR      0x02
-#define OMAP_MCBSP_REG_DXR      0x06
-#define OMAP_MCBSP_REG_SPCR2    0x08
-#define OMAP_MCBSP_REG_SPCR1    0x0a
-#define OMAP_MCBSP_REG_RCR2     0x0c
-#define OMAP_MCBSP_REG_RCR1     0x0e
-#define OMAP_MCBSP_REG_XCR2     0x10
-#define OMAP_MCBSP_REG_XCR1     0x12
-#define OMAP_MCBSP_REG_SRGR2    0x14
-#define OMAP_MCBSP_REG_SRGR1    0x16
-#define OMAP_MCBSP_REG_MCR2     0x18
-#define OMAP_MCBSP_REG_MCR1     0x1a
-#define OMAP_MCBSP_REG_RCERA    0x1c
-#define OMAP_MCBSP_REG_RCERB    0x1e
-#define OMAP_MCBSP_REG_XCERA    0x20
-#define OMAP_MCBSP_REG_XCERB    0x22
-#define OMAP_MCBSP_REG_PCR0     0x24
-#define OMAP_MCBSP_REG_RCERC    0x26
-#define OMAP_MCBSP_REG_RCERD    0x28
-#define OMAP_MCBSP_REG_XCERC    0x2A
-#define OMAP_MCBSP_REG_XCERD    0x2C
-#define OMAP_MCBSP_REG_RCERE    0x2E
-#define OMAP_MCBSP_REG_RCERF    0x30
-#define OMAP_MCBSP_REG_XCERE    0x32
-#define OMAP_MCBSP_REG_XCERF    0x34
-#define OMAP_MCBSP_REG_RCERG    0x36
-#define OMAP_MCBSP_REG_RCERH    0x38
-#define OMAP_MCBSP_REG_XCERG    0x3A
-#define OMAP_MCBSP_REG_XCERH    0x3C
-
-/* Dummy defines, these are not available on omap1 */
-#define OMAP_MCBSP_REG_XCCR     0x00
-#define OMAP_MCBSP_REG_RCCR     0x00
-
-#else
-
-#define OMAP_MCBSP_REG_DRR2     0x00
-#define OMAP_MCBSP_REG_DRR1     0x04
-#define OMAP_MCBSP_REG_DXR2     0x08
-#define OMAP_MCBSP_REG_DXR1     0x0C
-#define OMAP_MCBSP_REG_DRR      0x00
-#define OMAP_MCBSP_REG_DXR      0x08
-#define OMAP_MCBSP_REG_SPCR2    0x10
-#define OMAP_MCBSP_REG_SPCR1    0x14
-#define OMAP_MCBSP_REG_RCR2     0x18
-#define OMAP_MCBSP_REG_RCR1     0x1C
-#define OMAP_MCBSP_REG_XCR2     0x20
-#define OMAP_MCBSP_REG_XCR1     0x24
-#define OMAP_MCBSP_REG_SRGR2    0x28
-#define OMAP_MCBSP_REG_SRGR1    0x2C
-#define OMAP_MCBSP_REG_MCR2     0x30
-#define OMAP_MCBSP_REG_MCR1     0x34
-#define OMAP_MCBSP_REG_RCERA    0x38
-#define OMAP_MCBSP_REG_RCERB    0x3C
-#define OMAP_MCBSP_REG_XCERA    0x40
-#define OMAP_MCBSP_REG_XCERB    0x44
-#define OMAP_MCBSP_REG_PCR0     0x48
-#define OMAP_MCBSP_REG_RCERC    0x4C
-#define OMAP_MCBSP_REG_RCERD    0x50
-#define OMAP_MCBSP_REG_XCERC    0x54
-#define OMAP_MCBSP_REG_XCERD    0x58
-#define OMAP_MCBSP_REG_RCERE    0x5C
-#define OMAP_MCBSP_REG_RCERF    0x60
-#define OMAP_MCBSP_REG_XCERE    0x64
-#define OMAP_MCBSP_REG_XCERF    0x68
-#define OMAP_MCBSP_REG_RCERG    0x6C
-#define OMAP_MCBSP_REG_RCERH    0x70
-#define OMAP_MCBSP_REG_XCERG    0x74
-#define OMAP_MCBSP_REG_XCERH    0x78
-#define OMAP_MCBSP_REG_SYSCON   0x8C
-#define OMAP_MCBSP_REG_THRSH2   0x90
-#define OMAP_MCBSP_REG_THRSH1   0x94
-#define OMAP_MCBSP_REG_IRQST    0xA0
-#define OMAP_MCBSP_REG_IRQEN    0xA4
-#define OMAP_MCBSP_REG_WAKEUPEN 0xA8
-#define OMAP_MCBSP_REG_XCCR     0xAC
-#define OMAP_MCBSP_REG_RCCR     0xB0
-#define OMAP_MCBSP_REG_XBUFFSTAT        0xB4
-#define OMAP_MCBSP_REG_RBUFFSTAT        0xB8
-#define OMAP_MCBSP_REG_SSELCR   0xBC
+/* McBSP register numbers. Register address offset = num * reg_step */
+enum {
+        /* Common registers */
+        OMAP_MCBSP_REG_SPCR2 = 4,
+        OMAP_MCBSP_REG_SPCR1,
+        OMAP_MCBSP_REG_RCR2,
+        OMAP_MCBSP_REG_RCR1,
+        OMAP_MCBSP_REG_XCR2,
+        OMAP_MCBSP_REG_XCR1,
+        OMAP_MCBSP_REG_SRGR2,
+        OMAP_MCBSP_REG_SRGR1,
+        OMAP_MCBSP_REG_MCR2,
+        OMAP_MCBSP_REG_MCR1,
+        OMAP_MCBSP_REG_RCERA,
+        OMAP_MCBSP_REG_RCERB,
+        OMAP_MCBSP_REG_XCERA,
+        OMAP_MCBSP_REG_XCERB,
+        OMAP_MCBSP_REG_PCR0,
+        OMAP_MCBSP_REG_RCERC,
+        OMAP_MCBSP_REG_RCERD,
+        OMAP_MCBSP_REG_XCERC,
+        OMAP_MCBSP_REG_XCERD,
+        OMAP_MCBSP_REG_RCERE,
+        OMAP_MCBSP_REG_RCERF,
+        OMAP_MCBSP_REG_XCERE,
+        OMAP_MCBSP_REG_XCERF,
+        OMAP_MCBSP_REG_RCERG,
+        OMAP_MCBSP_REG_RCERH,
+        OMAP_MCBSP_REG_XCERG,
+        OMAP_MCBSP_REG_XCERH,
+
+        /* OMAP1-OMAP2420 registers */
+        OMAP_MCBSP_REG_DRR2 = 0,
+        OMAP_MCBSP_REG_DRR1,
+        OMAP_MCBSP_REG_DXR2,
+        OMAP_MCBSP_REG_DXR1,
+
+        /* OMAP2430 and onwards */
+        OMAP_MCBSP_REG_DRR = 0,
+        OMAP_MCBSP_REG_DXR = 2,
+        OMAP_MCBSP_REG_SYSCON = 35,
+        OMAP_MCBSP_REG_THRSH2,
+        OMAP_MCBSP_REG_THRSH1,
+        OMAP_MCBSP_REG_IRQST = 40,
+        OMAP_MCBSP_REG_IRQEN,
+        OMAP_MCBSP_REG_WAKEUPEN,
+        OMAP_MCBSP_REG_XCCR,
+        OMAP_MCBSP_REG_RCCR,
+        OMAP_MCBSP_REG_XBUFFSTAT,
+        OMAP_MCBSP_REG_RBUFFSTAT,
+        OMAP_MCBSP_REG_SSELCR,
+};
 
+/* OMAP3 sidetone control registers */
 #define OMAP_ST_REG_REV         0x00
 #define OMAP_ST_REG_SYSCONFIG   0x10
 #define OMAP_ST_REG_IRQSTATUS   0x18
@@ -146,8 +100,6 @@ static struct platform_device omap_mcbsp##port_nr = {	\
 #define OMAP_ST_REG_SFIRCR      0x28
 #define OMAP_ST_REG_SSELCR      0x2C
 
-#endif
-
 /************************** McBSP SPCR1 bit definitions ***********************/
 #define RRST                    0x0001
 #define RRDY                    0x0002
@@ -344,20 +296,20 @@ typedef enum {
 struct omap_mcbsp_ops {
         void (*request)(unsigned int);
         void (*free)(unsigned int);
-        int (*set_clks_src)(u8, u8);
 };
 
 struct omap_mcbsp_platform_data {
-        unsigned long phys_base;
-        u8 dma_rx_sync, dma_tx_sync;
-        u16 rx_irq, tx_irq;
         struct omap_mcbsp_ops *ops;
-#ifdef CONFIG_ARCH_OMAP3
-        /* Sidetone block for McBSP 2 and 3 */
-        unsigned long phys_base_st;
-#endif
         u16 buffer_size;
-        unsigned int mcbsp_config_type;
+        u8 reg_size;
+        u8 reg_step;
+
+        /* McBSP platform and instance specific features */
+        bool has_wakeup; /* Wakeup capability */
+        bool has_ccr; /* Transceiver has configuration control registers */
+        int (*enable_st_clock)(unsigned int, bool);
+        int (*set_clk_src)(struct device *dev, struct clk *clk, const char *src);
+        int (*mux_signal)(struct device *dev, const char *signal, const char *src);
 };
 
 struct omap_mcbsp_st_data {
@@ -389,14 +341,12 @@ struct omap_mcbsp {
         spinlock_t lock;
         struct omap_mcbsp_platform_data *pdata;
         struct clk *fclk;
-#ifdef CONFIG_ARCH_OMAP3
         struct omap_mcbsp_st_data *st_data;
         int dma_op_mode;
         u16 max_tx_thres;
         u16 max_rx_thres;
-#endif
         void *reg_cache;
-        unsigned int mcbsp_config_type;
+        int reg_cache_size;
 };
 
 /**
@@ -408,16 +358,10 @@ struct omap_mcbsp_dev_attr {
 };
 
 extern struct omap_mcbsp **mcbsp_ptr;
-extern int omap_mcbsp_count, omap_mcbsp_cache_size;
-
-#define omap_mcbsp_check_valid_id(id)   (id < omap_mcbsp_count)
-#define id_to_mcbsp_ptr(id)             mcbsp_ptr[id];
+extern int omap_mcbsp_count;
 
 int omap_mcbsp_init(void);
-void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
-                        struct omap_mcbsp_platform_data *config, int size);
 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
-#ifdef CONFIG_ARCH_OMAP3
 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
@@ -426,18 +370,6 @@ u16 omap_mcbsp_get_fifo_size(unsigned int id);
 u16 omap_mcbsp_get_tx_delay(unsigned int id);
 u16 omap_mcbsp_get_rx_delay(unsigned int id);
 int omap_mcbsp_get_dma_op_mode(unsigned int id);
-#else
-static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
-{ }
-static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
-{ }
-static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; }
-static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; }
-static inline u16 omap_mcbsp_get_fifo_size(unsigned int id) { return 0; }
-static inline u16 omap_mcbsp_get_tx_delay(unsigned int id) { return 0; }
-static inline u16 omap_mcbsp_get_rx_delay(unsigned int id) { return 0; }
-static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; }
-#endif
 int omap_mcbsp_request(unsigned int id);
 void omap_mcbsp_free(unsigned int id);
 void omap_mcbsp_start(unsigned int id, int tx, int rx);
@@ -453,21 +385,11 @@ void omap2_mcbsp1_mux_fsr_src(u8 mux);
 int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream);
 int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream);
 
-#ifdef CONFIG_ARCH_OMAP3
 /* Sidetone specific API */
 int omap_st_set_chgain(unsigned int id, int channel, s16 chgain);
 int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain);
 int omap_st_enable(unsigned int id);
 int omap_st_disable(unsigned int id);
 int omap_st_is_enabled(unsigned int id);
-#else
-static inline int omap_st_set_chgain(unsigned int id, int channel,
-                                     s16 chgain) { return 0; }
-static inline int omap_st_get_chgain(unsigned int id, int channel,
-                                     s16 *chgain) { return 0; }
-static inline int omap_st_enable(unsigned int id) { return 0; }
-static inline int omap_st_disable(unsigned int id) { return 0; }
-static inline int omap_st_is_enabled(unsigned int id) {  return 0; }
-#endif
 
 #endif
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index ee405b36df4b..12c5b0c345bf 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -68,7 +68,7 @@ extern struct device omap_device_parent;
  *
  */
 struct omap_device {
-        struct platform_device          pdev;
+        struct platform_device          *pdev;
         struct omap_hwmod               **hwmods;
         struct omap_device_pm_latency   *pm_lats;
         u32                             dev_wakeup_lat;
@@ -88,25 +88,20 @@ int omap_device_shutdown(struct platform_device *pdev);
 
 /* Core code interface */
 
-int omap_device_count_resources(struct omap_device *od);
-int omap_device_fill_resources(struct omap_device *od, struct resource *res);
-
-struct omap_device *omap_device_build(const char *pdev_name, int pdev_id,
+struct platform_device *omap_device_build(const char *pdev_name, int pdev_id,
                                       struct omap_hwmod *oh, void *pdata,
                                       int pdata_len,
                                       struct omap_device_pm_latency *pm_lats,
                                       int pm_lats_cnt, int is_early_device);
 
-struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
+struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
                                          struct omap_hwmod **oh, int oh_cnt,
                                          void *pdata, int pdata_len,
                                          struct omap_device_pm_latency *pm_lats,
                                          int pm_lats_cnt, int is_early_device);
 
-int omap_device_register(struct omap_device *od);
-int omap_early_device_register(struct omap_device *od);
-
 void __iomem *omap_device_get_rt_va(struct omap_device *od);
+struct device *omap_device_get_by_hwmod_name(const char *oh_name);
 
 /* OMAP PM interface */
 int omap_device_align_pm_lat(struct platform_device *pdev,
@@ -122,11 +117,6 @@ int omap_device_enable_hwmods(struct omap_device *od);
 int omap_device_disable_clocks(struct omap_device *od);
 int omap_device_enable_clocks(struct omap_device *od);
 
-static inline void omap_device_disable_idle_on_suspend(struct omap_device *od)
-{
-        od->flags |= OMAP_DEVICE_NO_IDLE_ON_SUSPEND;
-}
-
 /*
  * Entries should be kept in latency order ascending
  *
@@ -157,6 +147,17 @@ struct omap_device_pm_latency {
 #define OMAP_DEVICE_LATENCY_AUTO_ADJUST BIT(1)
 
 /* Get omap_device pointer from platform_device pointer */
-#define to_omap_device(x) container_of((x), struct omap_device, pdev)
+static inline struct omap_device *to_omap_device(struct platform_device *pdev)
+{
+        return pdev ? pdev->archdata.od : NULL;
+}
+
+static inline
+void omap_device_disable_idle_on_suspend(struct platform_device *pdev)
+{
+        struct omap_device *od = to_omap_device(pdev);
+
+        od->flags |= OMAP_DEVICE_NO_IDLE_ON_SUSPEND;
+}
 
 #endif
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 0e329ca88a70..5419f1a2aaa4 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -496,7 +496,6 @@ struct omap_hwmod_class {
  * @_state: internal-use hwmod state
  * @_postsetup_state: internal-use state to leave the hwmod in after _setup()
  * @flags: hwmod flags (documented below)
- * @omap_chip: OMAP chips this hwmod is present on
  * @_lock: spinlock serializing operations on this hwmod
  * @node: list node for hwmod list (internal use)
  *
@@ -526,7 +525,6 @@ struct omap_hwmod {
         char                            *clkdm_name;
         struct clockdomain              *clkdm;
         char                            *vdd_name;
-        struct voltagedomain            *voltdm;
         struct omap_hwmod_ocp_if        **masters; /* connect to *_IA */
         struct omap_hwmod_ocp_if        **slaves;  /* connect to *_TA */
         void                            *dev_attr;
@@ -545,7 +543,6 @@ struct omap_hwmod {
         u8                              _int_flags;
         u8                              _state;
         u8                              _postsetup_state;
-        const struct omap_chip_id       omap_chip;
 };
 
 int omap_hwmod_register(struct omap_hwmod **ohs);
diff --git a/arch/arm/plat-omap/include/plat/voltage.h b/arch/arm/plat-omap/include/plat/voltage.h
new file mode 100644
index 000000000000..0a6a482ec014
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/voltage.h
@@ -0,0 +1,20 @@
+/*
+ * OMAP Voltage Management Routines
+ *
+ * Copyright (C) 2011, Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_OMAP_VOLTAGE_H
+#define __ARCH_ARM_OMAP_VOLTAGE_H
+
+struct voltagedomain;
+
+struct voltagedomain *voltdm_lookup(const char *name);
+int voltdm_scale(struct voltagedomain *voltdm, unsigned long target_volt);
+unsigned long voltdm_get_voltage(struct voltagedomain *voltdm);
+
+#endif