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authorLinus Torvalds <torvalds@linux-foundation.org>2010-05-21 13:50:00 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2010-05-21 13:50:00 -0400
commita6f039869ff87e0a8d621e31d14bbb120c1dfa93 (patch)
treec8975a8d02893633d03efe5435aa8b0635298a93 /arch/arm/plat-omap/include/plat
parente0bc5d4a54938eedcde14005210e6c08aa9727e4 (diff)
parentf6304f5804f228b6c2fea9e3dfac25c5b2db9b38 (diff)
Merge branch 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6
* 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: (113 commits) omap4: Add support for i2c init omap: Fix i2c platform init code for omap4 OMAP2 clock: fix recursive spinlock attempt when CONFIG_CPU_FREQ=y OMAP powerdomain, hwmod, omap_device: add some credits OMAP4 powerdomain: Support LOWPOWERSTATECHANGE for powerdomains OMAP3 clock: add support for setting the divider for sys_clkout2 using clk_set_rate OMAP4 powerdomain: Fix pwrsts flags for ALWAYS ON domains OMAP: timers: Fix clock source names for OMAP4 OMAP4 clock: Support clk_set_parent OMAP4: PRCM: Add offset defines for all CM registers OMAP4: PRCM: Add offset defines for all PRM registers OMAP4: PRCM: Remove duplicate definition of base addresses OMAP4: PRM: Remove MPU internal code name and apply PRCM naming convention OMAP4: CM: Remove non-functional registers in ES1.0 OMAP: hwmod: Replace WARN by pr_warning for clockdomain check OMAP: hwmod: Rename hwmod name for the MPU OMAP: hwmod: Do not exit the iteration if one clock init failed OMAP: hwmod: Replace WARN by pr_warning if clock lookup failed OMAP: hwmod: Remove IS_ERR check with omap_clk_get_by_name return value OMAP: hwmod: Fix wrong pointer iteration in oh->slaves ...
Diffstat (limited to 'arch/arm/plat-omap/include/plat')
-rw-r--r--arch/arm/plat-omap/include/plat/clock.h14
-rw-r--r--arch/arm/plat-omap/include/plat/common.h3
-rw-r--r--arch/arm/plat-omap/include/plat/control.h20
-rw-r--r--arch/arm/plat-omap/include/plat/gpio.h4
-rw-r--r--arch/arm/plat-omap/include/plat/irqs.h4
-rw-r--r--arch/arm/plat-omap/include/plat/mmc.h4
-rw-r--r--arch/arm/plat-omap/include/plat/multi.h16
-rw-r--r--arch/arm/plat-omap/include/plat/omap44xx.h4
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h16
-rw-r--r--arch/arm/plat-omap/include/plat/powerdomain.h7
-rw-r--r--arch/arm/plat-omap/include/plat/serial.h16
-rw-r--r--arch/arm/plat-omap/include/plat/uncompress.h44
12 files changed, 100 insertions, 52 deletions
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 34f7fa9ad4c0..dfc472ca0cc4 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -196,15 +196,15 @@ extern struct clk dummy_ck;
196#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ 196#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
197 197
198/* Clksel_rate flags */ 198/* Clksel_rate flags */
199#define DEFAULT_RATE (1 << 0) 199#define RATE_IN_242X (1 << 0)
200#define RATE_IN_242X (1 << 1) 200#define RATE_IN_243X (1 << 1)
201#define RATE_IN_243X (1 << 2) 201#define RATE_IN_3XXX (1 << 2) /* rates common to all OMAP3 */
202#define RATE_IN_343X (1 << 3) /* rates common to all 343X */ 202#define RATE_IN_3430ES2 (1 << 3) /* 3430ES2 rates only */
203#define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */ 203#define RATE_IN_36XX (1 << 4)
204#define RATE_IN_36XX (1 << 5) 204#define RATE_IN_4430 (1 << 5)
205#define RATE_IN_4430 (1 << 6)
206 205
207#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) 206#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
208 207
208#define RATE_IN_3430ES2PLUS (RATE_IN_3430ES2 | RATE_IN_36XX)
209 209
210#endif 210#endif
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index 7556e271942e..d265018f5e6b 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -31,9 +31,6 @@
31 31
32struct sys_timer; 32struct sys_timer;
33 33
34/* used by omap-smp.c and board-4430sdp.c */
35extern void __iomem *gic_cpu_base_addr;
36
37extern void omap_map_common_io(void); 34extern void omap_map_common_io(void);
38extern struct sys_timer omap_timer; 35extern struct sys_timer omap_timer;
39 36
diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h
index a56deee97676..131bf405c2f6 100644
--- a/arch/arm/plat-omap/include/plat/control.h
+++ b/arch/arm/plat-omap/include/plat/control.h
@@ -207,6 +207,9 @@
207/* 44xx control status register offset */ 207/* 44xx control status register offset */
208#define OMAP44XX_CONTROL_STATUS 0x2c4 208#define OMAP44XX_CONTROL_STATUS 0x2c4
209 209
210/* 44xx-only CONTROL_GENERAL register offsets */
211#define OMAP44XX_CONTROL_MMC1 0x628
212#define OMAP44XX_CONTROL_PBIAS_LITE 0x600
210/* 213/*
211 * REVISIT: This list of registers is not comprehensive - there are more 214 * REVISIT: This list of registers is not comprehensive - there are more
212 * that should be added. 215 * that should be added.
@@ -252,6 +255,23 @@
252#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1) 255#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1)
253#define OMAP2_PBIASLITEVMODE0 (1 << 0) 256#define OMAP2_PBIASLITEVMODE0 (1 << 0)
254 257
258/* CONTROL_PBIAS_LITE bits for OMAP4 */
259#define OMAP4_MMC1_PWRDNZ (1 << 26)
260#define OMAP4_MMC1_PBIASLITE_HIZ_MODE (1 << 25)
261#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT (1 << 24)
262#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR (1 << 23)
263#define OMAP4_MMC1_PBIASLITE_PWRDNZ (1 << 22)
264#define OMAP4_MMC1_PBIASLITE_VMODE (1 << 21)
265#define OMAP4_USBC1_ICUSB_PWRDNZ (1 << 20)
266
267#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 (1 << 31)
268#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1 (1 << 30)
269#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 (1 << 29)
270#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3 (1 << 28)
271#define OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL (1 << 27)
272#define OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL (1 << 26)
273#define OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL (1 << 25)
274
255/* CONTROL_PROG_IO1 bits */ 275/* CONTROL_PROG_IO1 bits */
256#define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20) 276#define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20)
257 277
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index de7c54731cbe..de1c604962eb 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -72,8 +72,8 @@
72 IH_GPIO_BASE + (nr)) 72 IH_GPIO_BASE + (nr))
73 73
74extern int omap_gpio_init(void); /* Call from board init only */ 74extern int omap_gpio_init(void); /* Call from board init only */
75extern void omap2_gpio_prepare_for_retention(void); 75extern void omap2_gpio_prepare_for_idle(int power_state);
76extern void omap2_gpio_resume_after_retention(void); 76extern void omap2_gpio_resume_after_idle(void);
77extern void omap_set_gpio_debounce(int gpio, int enable); 77extern void omap_set_gpio_debounce(int gpio, int enable);
78extern void omap_set_gpio_debounce_time(int gpio, int enable); 78extern void omap_set_gpio_debounce_time(int gpio, int enable);
79extern void omap_gpio_save_context(void); 79extern void omap_gpio_save_context(void);
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 401701977dbb..c01d9f08a198 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -428,4 +428,8 @@ void omap3_intc_resume_idle(void);
428 428
429#include <mach/hardware.h> 429#include <mach/hardware.h>
430 430
431#ifdef CONFIG_FIQ
432#define FIQ_START 1024
433#endif
434
431#endif 435#endif
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index a1bac07c89eb..c835f1e994c6 100644
--- a/arch/arm/plat-omap/include/plat/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -102,6 +102,10 @@ struct omap_mmc_platform_data {
102 /* Regulator off remapped to sleep */ 102 /* Regulator off remapped to sleep */
103 unsigned vcc_aux_disable_is_sleep:1; 103 unsigned vcc_aux_disable_is_sleep:1;
104 104
105 /* we can put the features above into this variable */
106#define HSMMC_HAS_PBIAS (1 << 0)
107 unsigned features;
108
105 int switch_pin; /* gpio (card detect) */ 109 int switch_pin; /* gpio (card detect) */
106 int gpio_wp; /* gpio (write protect) */ 110 int gpio_wp; /* gpio (write protect) */
107 111
diff --git a/arch/arm/plat-omap/include/plat/multi.h b/arch/arm/plat-omap/include/plat/multi.h
index f235d32cd942..ffd909fa5287 100644
--- a/arch/arm/plat-omap/include/plat/multi.h
+++ b/arch/arm/plat-omap/include/plat/multi.h
@@ -61,9 +61,9 @@
61# define OMAP_NAME omap16xx 61# define OMAP_NAME omap16xx
62# endif 62# endif
63#endif 63#endif
64#if (defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)) 64#ifdef CONFIG_ARCH_OMAP2PLUS
65# if (defined(OMAP_NAME) || defined(MULTI_OMAP1)) 65# if (defined(OMAP_NAME) || defined(MULTI_OMAP1))
66# error "OMAP1 and OMAP2 can't be selected at the same time" 66# error "OMAP1 and OMAP2PLUS can't be selected at the same time"
67# endif 67# endif
68#endif 68#endif
69#ifdef CONFIG_ARCH_OMAP2420 69#ifdef CONFIG_ARCH_OMAP2420
@@ -82,12 +82,20 @@
82# define OMAP_NAME omap2430 82# define OMAP_NAME omap2430
83# endif 83# endif
84#endif 84#endif
85#ifdef CONFIG_ARCH_OMAP3430 85#ifdef CONFIG_ARCH_OMAP3
86# ifdef OMAP_NAME 86# ifdef OMAP_NAME
87# undef MULTI_OMAP2 87# undef MULTI_OMAP2
88# define MULTI_OMAP2 88# define MULTI_OMAP2
89# else 89# else
90# define OMAP_NAME omap3430 90# define OMAP_NAME omap3
91# endif
92#endif
93#ifdef CONFIG_ARCH_OMAP4
94# ifdef OMAP_NAME
95# undef MULTI_OMAP2
96# define MULTI_OMAP2
97# else
98# define OMAP_NAME omap4
91# endif 99# endif
92#endif 100#endif
93 101
diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h
index b3ef1a7f53cc..8b3f12ff5cbc 100644
--- a/arch/arm/plat-omap/include/plat/omap44xx.h
+++ b/arch/arm/plat-omap/include/plat/omap44xx.h
@@ -30,6 +30,7 @@
30#define OMAP4430_CM_BASE OMAP4430_CM1_BASE 30#define OMAP4430_CM_BASE OMAP4430_CM1_BASE
31#define OMAP4430_CM2_BASE 0x4a008000 31#define OMAP4430_CM2_BASE 0x4a008000
32#define OMAP4430_PRM_BASE 0x4a306000 32#define OMAP4430_PRM_BASE 0x4a306000
33#define OMAP4430_PRCM_MPU_BASE 0x48243000
33#define OMAP44XX_GPMC_BASE 0x50000000 34#define OMAP44XX_GPMC_BASE 0x50000000
34#define OMAP443X_SCM_BASE 0x4a002000 35#define OMAP443X_SCM_BASE 0x4a002000
35#define OMAP443X_CTRL_BASE 0x4a100000 36#define OMAP443X_CTRL_BASE 0x4a100000
@@ -48,5 +49,8 @@
48#define OMAP44XX_MAILBOX_BASE (L4_44XX_BASE + 0xF4000) 49#define OMAP44XX_MAILBOX_BASE (L4_44XX_BASE + 0xF4000)
49#define OMAP44XX_HSUSB_OTG_BASE (L4_44XX_BASE + 0xAB000) 50#define OMAP44XX_HSUSB_OTG_BASE (L4_44XX_BASE + 0xAB000)
50 51
52#define OMAP4_MMU1_BASE 0x55082000
53#define OMAP4_MMU2_BASE 0x4A066000
54
51#endif /* __ASM_ARCH_OMAP44XX_H */ 55#endif /* __ASM_ARCH_OMAP44XX_H */
52 56
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 36d6ea56ab51..0eccc09ac4a9 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -176,9 +176,8 @@ struct omap_hwmod_addr_space {
176#define OCP_USER_SDMA (1 << 1) 176#define OCP_USER_SDMA (1 << 1)
177 177
178/* omap_hwmod_ocp_if.flags bits */ 178/* omap_hwmod_ocp_if.flags bits */
179#define OCPIF_HAS_IDLEST (1 << 0) 179#define OCPIF_SWSUP_IDLE (1 << 0)
180#define OCPIF_SWSUP_IDLE (1 << 1) 180#define OCPIF_CAN_BURST (1 << 1)
181#define OCPIF_CAN_BURST (1 << 2)
182 181
183/** 182/**
184 * struct omap_hwmod_ocp_if - OCP interface data 183 * struct omap_hwmod_ocp_if - OCP interface data
@@ -327,14 +326,12 @@ struct omap_hwmod_omap2_prcm {
327 326
328/** 327/**
329 * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data 328 * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
330 * @module_offs: PRCM submodule offset from the start of the PRM/CM1/CM2 329 * @clkctrl_reg: PRCM address of the clock control register
331 * @device_offs: device register offset from @module_offs
332 * @submodule_wkdep_bit: bit shift of the WKDEP range 330 * @submodule_wkdep_bit: bit shift of the WKDEP range
333 */ 331 */
334struct omap_hwmod_omap4_prcm { 332struct omap_hwmod_omap4_prcm {
335 u32 module_offs; 333 void __iomem *clkctrl_reg;
336 u16 device_offs; 334 u8 submodule_wkdep_bit;
337 u8 submodule_wkdep_bit;
338}; 335};
339 336
340 337
@@ -353,6 +350,8 @@ struct omap_hwmod_omap4_prcm {
353 * when module is enabled, rather than the default, which is to 350 * when module is enabled, rather than the default, which is to
354 * enable autoidle 351 * enable autoidle
355 * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup 352 * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
353 * HWMOD_NO_IDLEST : this module does not have idle status - this is the case
354 * only for few initiator modules on OMAP2 & 3.
356 */ 355 */
357#define HWMOD_SWSUP_SIDLE (1 << 0) 356#define HWMOD_SWSUP_SIDLE (1 << 0)
358#define HWMOD_SWSUP_MSTANDBY (1 << 1) 357#define HWMOD_SWSUP_MSTANDBY (1 << 1)
@@ -360,6 +359,7 @@ struct omap_hwmod_omap4_prcm {
360#define HWMOD_INIT_NO_IDLE (1 << 3) 359#define HWMOD_INIT_NO_IDLE (1 << 3)
361#define HWMOD_NO_OCP_AUTOIDLE (1 << 4) 360#define HWMOD_NO_OCP_AUTOIDLE (1 << 4)
362#define HWMOD_SET_DEFAULT_CLOCKACT (1 << 5) 361#define HWMOD_SET_DEFAULT_CLOCKACT (1 << 5)
362#define HWMOD_NO_IDLEST (1 << 6)
363 363
364/* 364/*
365 * omap_hwmod._int_flags definitions 365 * omap_hwmod._int_flags definitions
diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h
index d82b2c00d4f1..fb6ec74fe39e 100644
--- a/arch/arm/plat-omap/include/plat/powerdomain.h
+++ b/arch/arm/plat-omap/include/plat/powerdomain.h
@@ -31,6 +31,7 @@
31#define PWRDM_MAX_PWRSTS 4 31#define PWRDM_MAX_PWRSTS 4
32 32
33/* Powerdomain allowable state bitfields */ 33/* Powerdomain allowable state bitfields */
34#define PWRSTS_ON (1 << PWRDM_POWER_ON)
34#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \ 35#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
35 (1 << PWRDM_POWER_ON)) 36 (1 << PWRDM_POWER_ON))
36 37
@@ -49,6 +50,12 @@
49 * in MEM bank 1 position. This is 50 * in MEM bank 1 position. This is
50 * true for OMAP3430 51 * true for OMAP3430
51 */ 52 */
53#define PWRDM_HAS_LOWPOWERSTATECHANGE (1 << 2) /*
54 * support to transition from a
55 * sleep state to a lower sleep
56 * state without waking up the
57 * powerdomain
58 */
52 59
53/* 60/*
54 * Number of memory banks that are power-controllable. On OMAP4430, the 61 * Number of memory banks that are power-controllable. On OMAP4430, the
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index 83dce4c4f7e6..19145f5c32ba 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -15,6 +15,20 @@
15 15
16#include <linux/init.h> 16#include <linux/init.h>
17 17
18/*
19 * Memory entry used for the DEBUG_LL UART configuration. See also
20 * uncompress.h and debug-macro.S.
21 *
22 * Note that using a memory location for storing the UART configuration
23 * has at least two limitations:
24 *
25 * 1. Kernel uncompress code cannot overlap OMAP_UART_INFO as the
26 * uncompress code could then partially overwrite itself
27 * 2. We assume printascii is called at least once before paging_init,
28 * and addruart has a chance to read OMAP_UART_INFO
29 */
30#define OMAP_UART_INFO (PHYS_OFFSET + 0x3ffc)
31
18/* OMAP1 serial ports */ 32/* OMAP1 serial ports */
19#define OMAP1_UART1_BASE 0xfffb0000 33#define OMAP1_UART1_BASE 0xfffb0000
20#define OMAP1_UART2_BASE 0xfffb0800 34#define OMAP1_UART2_BASE 0xfffb0800
@@ -39,7 +53,7 @@
39 53
40/* External port on Zoom2/3 */ 54/* External port on Zoom2/3 */
41#define ZOOM_UART_BASE 0x10000000 55#define ZOOM_UART_BASE 0x10000000
42#define ZOOM_UART_VIRT 0xfb000000 56#define ZOOM_UART_VIRT 0xfa400000
43 57
44#define OMAP_PORT_SHIFT 2 58#define OMAP_PORT_SHIFT 2
45#define OMAP7XX_PORT_SHIFT 0 59#define OMAP7XX_PORT_SHIFT 0
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index 81d9ec540fcf..bbedd71943f6 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -20,27 +20,21 @@
20#include <linux/types.h> 20#include <linux/types.h>
21#include <linux/serial_reg.h> 21#include <linux/serial_reg.h>
22 22
23#include <asm/memory.h>
23#include <asm/mach-types.h> 24#include <asm/mach-types.h>
24 25
25#include <plat/serial.h> 26#include <plat/serial.h>
26 27
27static volatile u8 *uart1_base;
28static int uart1_shift;
29
30static volatile u8 *uart_base; 28static volatile u8 *uart_base;
31static int uart_shift; 29static int uart_shift;
32 30
33/* 31/*
34 * Store the DEBUG_LL uart number into UART1 scratchpad register. 32 * Store the DEBUG_LL uart number into memory.
35 * See also debug-macro.S, and serial.c for related code. 33 * See also debug-macro.S, and serial.c for related code.
36 *
37 * Please note that we currently assume that:
38 * - UART1 clocks are enabled for register access
39 * - UART1 scratchpad register can be used
40 */ 34 */
41static void set_uart1_scratchpad(unsigned char port) 35static void set_omap_uart_info(unsigned char port)
42{ 36{
43 uart1_base[UART_SCR << uart1_shift] = port; 37 *(volatile u32 *)OMAP_UART_INFO = port;
44} 38}
45 39
46static void putc(int c) 40static void putc(int c)
@@ -60,42 +54,38 @@ static inline void flush(void)
60/* 54/*
61 * Macros to configure UART1 and debug UART 55 * Macros to configure UART1 and debug UART
62 */ 56 */
63#define _DEBUG_LL_ENTRY(mach, uart1_phys, uart1_shft, \ 57#define _DEBUG_LL_ENTRY(mach, dbg_uart, dbg_shft, dbg_id) \
64 dbg_uart, dbg_shft, dbg_id) \
65 if (machine_is_##mach()) { \ 58 if (machine_is_##mach()) { \
66 uart1_base = (volatile u8 *)(uart1_phys); \
67 uart1_shift = (uart1_shft); \
68 uart_base = (volatile u8 *)(dbg_uart); \ 59 uart_base = (volatile u8 *)(dbg_uart); \
69 uart_shift = (dbg_shft); \ 60 uart_shift = (dbg_shft); \
70 port = (dbg_id); \ 61 port = (dbg_id); \
71 set_uart1_scratchpad(port); \ 62 set_omap_uart_info(port); \
72 break; \ 63 break; \
73 } 64 }
74 65
75#define DEBUG_LL_OMAP7XX(p, mach) \ 66#define DEBUG_LL_OMAP7XX(p, mach) \
76 _DEBUG_LL_ENTRY(mach, OMAP1_UART1_BASE, OMAP7XX_PORT_SHIFT, \ 67 _DEBUG_LL_ENTRY(mach, OMAP1_UART##p##_BASE, OMAP7XX_PORT_SHIFT, \
77 OMAP1_UART##p##_BASE, OMAP7XX_PORT_SHIFT, OMAP1UART##p) 68 OMAP1UART##p)
78 69
79#define DEBUG_LL_OMAP1(p, mach) \ 70#define DEBUG_LL_OMAP1(p, mach) \
80 _DEBUG_LL_ENTRY(mach, OMAP1_UART1_BASE, OMAP_PORT_SHIFT, \ 71 _DEBUG_LL_ENTRY(mach, OMAP1_UART##p##_BASE, OMAP_PORT_SHIFT, \
81 OMAP1_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP1UART##p) 72 OMAP1UART##p)
82 73
83#define DEBUG_LL_OMAP2(p, mach) \ 74#define DEBUG_LL_OMAP2(p, mach) \
84 _DEBUG_LL_ENTRY(mach, OMAP2_UART1_BASE, OMAP_PORT_SHIFT, \ 75 _DEBUG_LL_ENTRY(mach, OMAP2_UART##p##_BASE, OMAP_PORT_SHIFT, \
85 OMAP2_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP2UART##p) 76 OMAP2UART##p)
86 77
87#define DEBUG_LL_OMAP3(p, mach) \ 78#define DEBUG_LL_OMAP3(p, mach) \
88 _DEBUG_LL_ENTRY(mach, OMAP3_UART1_BASE, OMAP_PORT_SHIFT, \ 79 _DEBUG_LL_ENTRY(mach, OMAP3_UART##p##_BASE, OMAP_PORT_SHIFT, \
89 OMAP3_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP3UART##p) 80 OMAP3UART##p)
90 81
91#define DEBUG_LL_OMAP4(p, mach) \ 82#define DEBUG_LL_OMAP4(p, mach) \
92 _DEBUG_LL_ENTRY(mach, OMAP4_UART1_BASE, OMAP_PORT_SHIFT, \ 83 _DEBUG_LL_ENTRY(mach, OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT, \
93 OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT, OMAP4UART##p) 84 OMAP4UART##p)
94 85
95/* Zoom2/3 shift is different for UART1 and external port */ 86/* Zoom2/3 shift is different for UART1 and external port */
96#define DEBUG_LL_ZOOM(mach) \ 87#define DEBUG_LL_ZOOM(mach) \
97 _DEBUG_LL_ENTRY(mach, OMAP2_UART1_BASE, OMAP_PORT_SHIFT, \ 88 _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
98 ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
99 89
100static inline void __arch_decomp_setup(unsigned long arch_id) 90static inline void __arch_decomp_setup(unsigned long arch_id)
101{ 91{
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