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authorTony Lindgren <tony@atomide.com>2009-10-20 12:40:47 -0400
committerTony Lindgren <tony@atomide.com>2009-10-20 12:40:47 -0400
commitce491cf85466c3377228c5a852ea627ec5136956 (patch)
tree3396aa3dc80ac30de662b59218d3bf788d105996 /arch/arm/plat-omap/include/plat/gpmc.h
parent3eff851b9dc1e84aa0822772e0be9afb0c973585 (diff)
omap: headers: Move remaining headers from include/mach to include/plat
Move the remaining headers under plat-omap/include/mach to plat-omap/include/plat. Also search and replace the files using these headers to include using the right path. This was done with: #!/bin/bash mach_dir_old="arch/arm/plat-omap/include/mach" plat_dir_new="arch/arm/plat-omap/include/plat" headers=$(cd $mach_dir_old && ls *.h) omap_dirs="arch/arm/*omap*/ \ drivers/video/omap \ sound/soc/omap" other_files="drivers/leds/leds-ams-delta.c \ drivers/mfd/menelaus.c \ drivers/mfd/twl4030-core.c \ drivers/mtd/nand/ams-delta.c" for header in $headers; do old="#include <mach\/$header" new="#include <plat\/$header" for dir in $omap_dirs; do find $dir -type f -name \*.[chS] | \ xargs sed -i "s/$old/$new/" done find drivers/ -type f -name \*omap*.[chS] | \ xargs sed -i "s/$old/$new/" for file in $other_files; do sed -i "s/$old/$new/" $file done done for header in $(ls $mach_dir_old/*.h); do git mv $header $plat_dir_new/ done Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/plat-omap/include/plat/gpmc.h')
-rw-r--r--arch/arm/plat-omap/include/plat/gpmc.h112
1 files changed, 112 insertions, 0 deletions
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
new file mode 100644
index 000000000000..9c99cda77ba6
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -0,0 +1,112 @@
1/*
2 * General-Purpose Memory Controller for OMAP2
3 *
4 * Copyright (C) 2005-2006 Nokia Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __OMAP2_GPMC_H
12#define __OMAP2_GPMC_H
13
14/* Maximum Number of Chip Selects */
15#define GPMC_CS_NUM 8
16
17#define GPMC_CS_CONFIG1 0x00
18#define GPMC_CS_CONFIG2 0x04
19#define GPMC_CS_CONFIG3 0x08
20#define GPMC_CS_CONFIG4 0x0c
21#define GPMC_CS_CONFIG5 0x10
22#define GPMC_CS_CONFIG6 0x14
23#define GPMC_CS_CONFIG7 0x18
24#define GPMC_CS_NAND_COMMAND 0x1c
25#define GPMC_CS_NAND_ADDRESS 0x20
26#define GPMC_CS_NAND_DATA 0x24
27
28#define GPMC_CONFIG 0x50
29#define GPMC_STATUS 0x54
30
31#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
32#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
33#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
34#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
35#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
36#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
37#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
38#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
39#define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
40#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
41#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
42#define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
43#define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
44#define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
45#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
46#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
47#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
48#define GPMC_CONFIG1_DEVICETYPE_NAND GPMC_CONFIG1_DEVICETYPE(1)
49#define GPMC_CONFIG1_MUXADDDATA (1 << 9)
50#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
51#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
52#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
53#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
54#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
55
56/*
57 * Note that all values in this struct are in nanoseconds, while
58 * the register values are in gpmc_fck cycles.
59 */
60struct gpmc_timings {
61 /* Minimum clock period for synchronous mode */
62 u16 sync_clk;
63
64 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
65 u16 cs_on; /* Assertion time */
66 u16 cs_rd_off; /* Read deassertion time */
67 u16 cs_wr_off; /* Write deassertion time */
68
69 /* ADV signal timings corresponding to GPMC_CONFIG3 */
70 u16 adv_on; /* Assertion time */
71 u16 adv_rd_off; /* Read deassertion time */
72 u16 adv_wr_off; /* Write deassertion time */
73
74 /* WE signals timings corresponding to GPMC_CONFIG4 */
75 u16 we_on; /* WE assertion time */
76 u16 we_off; /* WE deassertion time */
77
78 /* OE signals timings corresponding to GPMC_CONFIG4 */
79 u16 oe_on; /* OE assertion time */
80 u16 oe_off; /* OE deassertion time */
81
82 /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
83 u16 page_burst_access; /* Multiple access word delay */
84 u16 access; /* Start-cycle to first data valid delay */
85 u16 rd_cycle; /* Total read cycle time */
86 u16 wr_cycle; /* Total write cycle time */
87
88 /* The following are only on OMAP3430 */
89 u16 wr_access; /* WRACCESSTIME */
90 u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */
91};
92
93extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
94extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
95extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
96extern unsigned long gpmc_get_fclk_period(void);
97
98extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
99extern u32 gpmc_cs_read_reg(int cs, int idx);
100extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk);
101extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
102extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
103extern void gpmc_cs_free(int cs);
104extern int gpmc_cs_set_reserved(int cs, int reserved);
105extern int gpmc_cs_reserved(int cs);
106extern int gpmc_prefetch_enable(int cs, int dma_mode,
107 unsigned int u32_count, int is_write);
108extern void gpmc_prefetch_reset(void);
109extern int gpmc_prefetch_status(void);
110extern void __init gpmc_init(void);
111
112#endif