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authorTony Lindgren <tony@atomide.com>2008-12-10 20:37:17 -0500
committerTony Lindgren <tony@atomide.com>2008-12-10 20:37:17 -0500
commit90c62bf08f5823faa097271f3346a9142769b9ac (patch)
treeaa3bf442380815268b03092fd4b9c47924f9c3ee /arch/arm/plat-omap/include/mach
parentd88746652b4d133284d1fdd05b5e999e8f44c998 (diff)
omap mmc: Add low-level initialization for hsmmc controller
Add low-level initialization for hsmmc controller. Merged into this patch patch are various improvments and board support by Grazvydas Ignotas and David Brownell. Also change wire4 to be wires, as some newer controllers support 8 data lines. Cc: Pierre Ossman <drzeus-mmc@drzeus.cx> Signed-off-by: Grazvydas Ignotas <notasas@gmail.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/plat-omap/include/mach')
-rw-r--r--arch/arm/plat-omap/include/mach/control.h17
-rw-r--r--arch/arm/plat-omap/include/mach/mmc.h16
2 files changed, 25 insertions, 8 deletions
diff --git a/arch/arm/plat-omap/include/mach/control.h b/arch/arm/plat-omap/include/mach/control.h
index dc9886760577..269147f3836f 100644
--- a/arch/arm/plat-omap/include/mach/control.h
+++ b/arch/arm/plat-omap/include/mach/control.h
@@ -74,6 +74,7 @@
74#define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) 74#define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
75#define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) 75#define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
76#define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198) 76#define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198)
77#define OMAP243X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x0230)
77 78
78/* 24xx-only CONTROL_GENERAL register offsets */ 79/* 24xx-only CONTROL_GENERAL register offsets */
79#define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000) 80#define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000)
@@ -140,6 +141,7 @@
140#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) 141#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc)
141#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) 142#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
142#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) 143#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
144#define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02b0)
143#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02b4) 145#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02b4)
144 146
145/* 147/*
@@ -154,11 +156,14 @@
154 * and the security mode (secure, non-secure, don't care) 156 * and the security mode (secure, non-secure, don't care)
155 */ 157 */
156/* CONTROL_DEVCONF0 bits */ 158/* CONTROL_DEVCONF0 bits */
159#define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */
157#define OMAP24XX_USBSTANDBYCTRL (1 << 15) 160#define OMAP24XX_USBSTANDBYCTRL (1 << 15)
158#define OMAP2_MCBSP2_CLKS_MASK (1 << 6) 161#define OMAP2_MCBSP2_CLKS_MASK (1 << 6)
159#define OMAP2_MCBSP1_CLKS_MASK (1 << 2) 162#define OMAP2_MCBSP1_CLKS_MASK (1 << 2)
160 163
161/* CONTROL_DEVCONF1 bits */ 164/* CONTROL_DEVCONF1 bits */
165#define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 << 31)
166#define OMAP2_MMCSDIO2ADPCLKISEL (1 << 6) /* MMC2 loop back clock */
162#define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */ 167#define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */
163#define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */ 168#define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */
164#define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */ 169#define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */
@@ -172,6 +177,18 @@
172#define OMAP2_SYSBOOT_1_MASK (1 << 1) 177#define OMAP2_SYSBOOT_1_MASK (1 << 1)
173#define OMAP2_SYSBOOT_0_MASK (1 << 0) 178#define OMAP2_SYSBOOT_0_MASK (1 << 0)
174 179
180/* CONTROL_PBIAS_LITE bits */
181#define OMAP343X_PBIASLITESUPPLY_HIGH1 (1 << 15)
182#define OMAP343X_PBIASLITEVMODEERROR1 (1 << 11)
183#define OMAP343X_PBIASSPEEDCTRL1 (1 << 10)
184#define OMAP343X_PBIASLITEPWRDNZ1 (1 << 9)
185#define OMAP343X_PBIASLITEVMODE1 (1 << 8)
186#define OMAP343X_PBIASLITESUPPLY_HIGH0 (1 << 7)
187#define OMAP343X_PBIASLITEVMODEERROR0 (1 << 3)
188#define OMAP2_PBIASSPEEDCTRL0 (1 << 2)
189#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1)
190#define OMAP2_PBIASLITEVMODE0 (1 << 0)
191
175#ifndef __ASSEMBLY__ 192#ifndef __ASSEMBLY__
176#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 193#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
177extern void __iomem *omap_ctrl_base_get(void); 194extern void __iomem *omap_ctrl_base_get(void);
diff --git a/arch/arm/plat-omap/include/mach/mmc.h b/arch/arm/plat-omap/include/mach/mmc.h
index 0c2ef3b8956a..031250f02805 100644
--- a/arch/arm/plat-omap/include/mach/mmc.h
+++ b/arch/arm/plat-omap/include/mach/mmc.h
@@ -61,6 +61,11 @@ struct omap_mmc_platform_data {
61 61
62 struct omap_mmc_slot_data { 62 struct omap_mmc_slot_data {
63 63
64 /* 4 wire signaling is optional, and is used for SD/SDIO/HSMMC;
65 * 8 wire signaling is also optional, and is used with HSMMC
66 */
67 u8 wires;
68
64 /* 69 /*
65 * nomux means "standard" muxing is wrong on this board, and 70 * nomux means "standard" muxing is wrong on this board, and
66 * that board-specific code handled it before common init logic. 71 * that board-specific code handled it before common init logic.
@@ -70,13 +75,12 @@ struct omap_mmc_platform_data {
70 /* switch pin can be for card detect (default) or card cover */ 75 /* switch pin can be for card detect (default) or card cover */
71 unsigned cover:1; 76 unsigned cover:1;
72 77
73 /* 4 wire signaling is optional, and is only used for SD/SDIO */
74 unsigned wire4:1;
75
76 /* use the internal clock */ 78 /* use the internal clock */
77 unsigned internal_clock:1; 79 unsigned internal_clock:1;
78 s16 power_pin; 80 s16 power_pin;
79 s16 switch_pin; 81
82 int switch_pin; /* gpio (card detect) */
83 int gpio_wp; /* gpio (write protect) */
80 84
81 int (* set_bus_mode)(struct device *dev, int slot, int bus_mode); 85 int (* set_bus_mode)(struct device *dev, int slot, int bus_mode);
82 int (* set_power)(struct device *dev, int slot, int power_on, int vdd); 86 int (* set_power)(struct device *dev, int slot, int power_on, int vdd);
@@ -111,7 +115,6 @@ void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
111 int nr_controllers); 115 int nr_controllers);
112void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, 116void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
113 int nr_controllers); 117 int nr_controllers);
114void hsmmc_init(int controller_mask);
115int omap_mmc_add(int id, unsigned long base, unsigned long size, 118int omap_mmc_add(int id, unsigned long base, unsigned long size,
116 unsigned int irq, struct omap_mmc_platform_data *data); 119 unsigned int irq, struct omap_mmc_platform_data *data);
117#else 120#else
@@ -123,9 +126,6 @@ static inline void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
123 int nr_controllers) 126 int nr_controllers)
124{ 127{
125} 128}
126static inline void hsmmc_init(int controller_mask)
127{
128}
129static inline int omap_mmc_add(int id, unsigned long base, unsigned long size, 129static inline int omap_mmc_add(int id, unsigned long base, unsigned long size,
130 unsigned int irq, struct omap_mmc_platform_data *data) 130 unsigned int irq, struct omap_mmc_platform_data *data)
131{ 131{