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authorCory Maccarrone <darkstar6262@gmail.com>2010-01-08 13:29:04 -0500
committerTony Lindgren <tony@atomide.com>2010-01-08 13:29:04 -0500
commit4318f36b7c93a60a100f43fc6b7f13bebc59d017 (patch)
treed27ce211e4737febc9b1bca18e3fc0dac8045b62 /arch/arm/plat-omap/gpio.c
parent1866b54525d13402b2d129b906c4d189377f89c5 (diff)
omap: gpio: Simultaneously requested rising and falling edge
Some chips, namely any OMAP1 chips using METHOD_MPUIO, OMAP15xx and OMAP7xx, cannot be setup to respond to on-chip GPIO interrupts in both rising and falling edge directions -- they can only respond to one direction or the other, depending on how the ICR is configured. Additionally, current code forces rising edge detection if both flags are specified: if (trigger & IRQ_TYPE_EDGE_RISING) l |= 1 << gpio; else if (trigger & IRQ_TYPE_EDGE_FALLING) l &= ~(1 << gpio); else goto bad; This change implements a toggle function that will modify the ICR to flip the direction of interrupt for IRQs that are requested with both rising and falling flags. The toggle function is not called for chips and GPIOs it does not apply to through the use of a flip_mask that's added on a per-bank basis. The mask is only set for those GPIOs where a toggle is necessary. Edge detection starts out the same as above with FALLING mode first. The toggle happens on EACH interrupt; without it, we have the following sequence of actions on GPIO transition: ICR GPIO Result 0x1 0 -> 1 (rising) Interrupt 0x1 1 -> 0 (falling) No interrupt (set ICR to 0x0 manually) 0x0 0 -> 1 (rising) No interrupt 0x0 1 -> 0 (falling) Interrupt That is, with the ICR set to 1 for a gpio, only rising edge interrupts are caught, and with it set to 0, only falling edge interrupts are caught. If we add in the toggle, we get this: ICR GPIO Result 0x1 0 -> 1 (rising) Interrupt (ICR set to 0x0) 0x0 1 -> 0 (falling) Interrupt (ICR set to 0x1) 0x1 0 -> 1 ... so, both rising and falling are caught, per the request for both (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING). Signed-off-by: Cory Maccarrone <darkstar6262@gmail.com> Acked-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/plat-omap/gpio.c')
-rw-r--r--arch/arm/plat-omap/gpio.c61
1 files changed, 60 insertions, 1 deletions
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 04846811d0aa..f8dfa8d5e605 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -192,6 +192,7 @@ struct gpio_bank {
192 u32 saved_risingdetect; 192 u32 saved_risingdetect;
193#endif 193#endif
194 u32 level_mask; 194 u32 level_mask;
195 u32 toggle_mask;
195 spinlock_t lock; 196 spinlock_t lock;
196 struct gpio_chip chip; 197 struct gpio_chip chip;
197 struct clk *dbck; 198 struct clk *dbck;
@@ -749,6 +750,44 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
749} 750}
750#endif 751#endif
751 752
753/*
754 * This only applies to chips that can't do both rising and falling edge
755 * detection at once. For all other chips, this function is a noop.
756 */
757static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
758{
759 void __iomem *reg = bank->base;
760 u32 l = 0;
761
762 switch (bank->method) {
763#ifdef CONFIG_ARCH_OMAP1
764 case METHOD_MPUIO:
765 reg += OMAP_MPUIO_GPIO_INT_EDGE;
766 break;
767#endif
768#ifdef CONFIG_ARCH_OMAP15XX
769 case METHOD_GPIO_1510:
770 reg += OMAP1510_GPIO_INT_CONTROL;
771 break;
772#endif
773#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
774 case METHOD_GPIO_7XX:
775 reg += OMAP7XX_GPIO_INT_CONTROL;
776 break;
777#endif
778 default:
779 return;
780 }
781
782 l = __raw_readl(reg);
783 if ((l >> gpio) & 1)
784 l &= ~(1 << gpio);
785 else
786 l |= 1 << gpio;
787
788 __raw_writel(l, reg);
789}
790
752static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) 791static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
753{ 792{
754 void __iomem *reg = bank->base; 793 void __iomem *reg = bank->base;
@@ -759,6 +798,8 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
759 case METHOD_MPUIO: 798 case METHOD_MPUIO:
760 reg += OMAP_MPUIO_GPIO_INT_EDGE; 799 reg += OMAP_MPUIO_GPIO_INT_EDGE;
761 l = __raw_readl(reg); 800 l = __raw_readl(reg);
801 if (trigger & IRQ_TYPE_EDGE_BOTH)
802 bank->toggle_mask |= 1 << gpio;
762 if (trigger & IRQ_TYPE_EDGE_RISING) 803 if (trigger & IRQ_TYPE_EDGE_RISING)
763 l |= 1 << gpio; 804 l |= 1 << gpio;
764 else if (trigger & IRQ_TYPE_EDGE_FALLING) 805 else if (trigger & IRQ_TYPE_EDGE_FALLING)
@@ -771,6 +812,8 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
771 case METHOD_GPIO_1510: 812 case METHOD_GPIO_1510:
772 reg += OMAP1510_GPIO_INT_CONTROL; 813 reg += OMAP1510_GPIO_INT_CONTROL;
773 l = __raw_readl(reg); 814 l = __raw_readl(reg);
815 if (trigger & IRQ_TYPE_EDGE_BOTH)
816 bank->toggle_mask |= 1 << gpio;
774 if (trigger & IRQ_TYPE_EDGE_RISING) 817 if (trigger & IRQ_TYPE_EDGE_RISING)
775 l |= 1 << gpio; 818 l |= 1 << gpio;
776 else if (trigger & IRQ_TYPE_EDGE_FALLING) 819 else if (trigger & IRQ_TYPE_EDGE_FALLING)
@@ -803,6 +846,8 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
803 case METHOD_GPIO_7XX: 846 case METHOD_GPIO_7XX:
804 reg += OMAP7XX_GPIO_INT_CONTROL; 847 reg += OMAP7XX_GPIO_INT_CONTROL;
805 l = __raw_readl(reg); 848 l = __raw_readl(reg);
849 if (trigger & IRQ_TYPE_EDGE_BOTH)
850 bank->toggle_mask |= 1 << gpio;
806 if (trigger & IRQ_TYPE_EDGE_RISING) 851 if (trigger & IRQ_TYPE_EDGE_RISING)
807 l |= 1 << gpio; 852 l |= 1 << gpio;
808 else if (trigger & IRQ_TYPE_EDGE_FALLING) 853 else if (trigger & IRQ_TYPE_EDGE_FALLING)
@@ -1217,7 +1262,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1217{ 1262{
1218 void __iomem *isr_reg = NULL; 1263 void __iomem *isr_reg = NULL;
1219 u32 isr; 1264 u32 isr;
1220 unsigned int gpio_irq; 1265 unsigned int gpio_irq, gpio_index;
1221 struct gpio_bank *bank; 1266 struct gpio_bank *bank;
1222 u32 retrigger = 0; 1267 u32 retrigger = 0;
1223 int unmasked = 0; 1268 int unmasked = 0;
@@ -1284,9 +1329,23 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1284 1329
1285 gpio_irq = bank->virtual_irq_start; 1330 gpio_irq = bank->virtual_irq_start;
1286 for (; isr != 0; isr >>= 1, gpio_irq++) { 1331 for (; isr != 0; isr >>= 1, gpio_irq++) {
1332 gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
1333
1287 if (!(isr & 1)) 1334 if (!(isr & 1))
1288 continue; 1335 continue;
1289 1336
1337#ifdef CONFIG_ARCH_OMAP1
1338 /*
1339 * Some chips can't respond to both rising and falling
1340 * at the same time. If this irq was requested with
1341 * both flags, we need to flip the ICR data for the IRQ
1342 * to respond to the IRQ for the opposite direction.
1343 * This will be indicated in the bank toggle_mask.
1344 */
1345 if (bank->toggle_mask & (1 << gpio_index))
1346 _toggle_gpio_edge_triggering(bank, gpio_index);
1347#endif
1348
1290 generic_handle_irq(gpio_irq); 1349 generic_handle_irq(gpio_irq);
1291 } 1350 }
1292 } 1351 }