ARM: OMAP4: Add minimal support for omap4

This patch adds the support for OMAP4. The platform and machine specific
headers and sources updated for OMAP4430 SDP platform.

OMAP4430 is Texas Instrument's SOC based on ARM Cortex-A9 SMP architecture.
It's a dual core SOC with GIC used for interrupt handling and SCU for cache
coherency.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

1 files changed, 56 insertions, 3 deletions

diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index ee206122f507..7f50b6103dee 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -7,6 +7,9 @@
  * OMAP2 support by Juha Yrjola
  * API improvements and OMAP2 clock framework support by Timo Teras
  *
+ * Copyright (C) 2009 Texas Instruments
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License as published by the
  * Free Software Foundation; either version 2 of the License, or (at your
@@ -150,7 +153,8 @@
 struct omap_dm_timer {
         unsigned long phys_base;
         int irq;
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
+                        defined(CONFIG_ARCH_OMAP4)
         struct clk *iclk, *fclk;
 #endif
         void __iomem *io_base;
@@ -169,6 +173,9 @@ struct omap_dm_timer {
 #define omap3_dm_timers                 NULL
 #define omap3_dm_source_names           NULL
 #define omap3_dm_source_clocks          NULL
+#define omap4_dm_timers                 NULL
+#define omap4_dm_source_names           NULL
+#define omap4_dm_source_clocks          NULL
 
 static struct omap_dm_timer omap1_dm_timers[] = {
         { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
@@ -191,6 +198,9 @@ static const int dm_timer_count = ARRAY_SIZE(omap1_dm_timers);
 #define omap3_dm_timers                 NULL
 #define omap3_dm_source_names           NULL
 #define omap3_dm_source_clocks          NULL
+#define omap4_dm_timers                 NULL
+#define omap4_dm_source_names           NULL
+#define omap4_dm_source_clocks          NULL
 
 static struct omap_dm_timer omap2_dm_timers[] = {
         { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
@@ -225,6 +235,9 @@ static const int dm_timer_count = ARRAY_SIZE(omap2_dm_timers);
 #define omap2_dm_timers                 NULL
 #define omap2_dm_source_names           NULL
 #define omap2_dm_source_clocks          NULL
+#define omap4_dm_timers                 NULL
+#define omap4_dm_source_names           NULL
+#define omap4_dm_source_clocks          NULL
 
 static struct omap_dm_timer omap3_dm_timers[] = {
         { .phys_base = 0x48318000, .irq = INT_24XX_GPTIMER1 },
@@ -250,6 +263,40 @@ static const char *omap3_dm_source_names[] __initdata = {
 static struct clk *omap3_dm_source_clocks[2];
 static const int dm_timer_count = ARRAY_SIZE(omap3_dm_timers);
 
+#elif defined(CONFIG_ARCH_OMAP4)
+
+#define omap_dm_clk_enable(x)           clk_enable(x)
+#define omap_dm_clk_disable(x)          clk_disable(x)
+#define omap1_dm_timers                 NULL
+#define omap2_dm_timers                 NULL
+#define omap2_dm_source_names           NULL
+#define omap2_dm_source_clocks          NULL
+#define omap3_dm_timers                 NULL
+#define omap3_dm_source_names           NULL
+#define omap3_dm_source_clocks          NULL
+
+static struct omap_dm_timer omap4_dm_timers[] = {
+        { .phys_base = 0x4a318000, .irq = INT_44XX_GPTIMER1 },
+        { .phys_base = 0x48032000, .irq = INT_44XX_GPTIMER2 },
+        { .phys_base = 0x48034000, .irq = INT_44XX_GPTIMER3 },
+        { .phys_base = 0x48036000, .irq = INT_44XX_GPTIMER4 },
+        { .phys_base = 0x40138000, .irq = INT_44XX_GPTIMER5 },
+        { .phys_base = 0x4013a000, .irq = INT_44XX_GPTIMER6 },
+        { .phys_base = 0x4013a000, .irq = INT_44XX_GPTIMER7 },
+        { .phys_base = 0x4013e000, .irq = INT_44XX_GPTIMER8 },
+        { .phys_base = 0x4803e000, .irq = INT_44XX_GPTIMER9 },
+        { .phys_base = 0x48086000, .irq = INT_44XX_GPTIMER10 },
+        { .phys_base = 0x48088000, .irq = INT_44XX_GPTIMER11 },
+        { .phys_base = 0x4a320000, .irq = INT_44XX_GPTIMER12 },
+};
+static const char *omap4_dm_source_names[] __initdata = {
+        "sys_ck",
+        "omap_32k_fck",
+        NULL
+};
+static struct clk *omap4_dm_source_clocks[2];
+static const int dm_timer_count = ARRAY_SIZE(omap4_dm_timers);
+
 #else
 
 #error OMAP architecture not supported!
@@ -459,7 +506,8 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
 
-#elif defined(CONFIG_ARCH_OMAP2) || defined (CONFIG_ARCH_OMAP3)
+#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
+                                defined(CONFIG_ARCH_OMAP4)
 
 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
 {
@@ -711,6 +759,10 @@ int __init omap_dm_timer_init(void)
                 dm_timers = omap3_dm_timers;
                 dm_source_names = omap3_dm_source_names;
                 dm_source_clocks = omap3_dm_source_clocks;
+        } else if (cpu_is_omap44xx()) {
+                dm_timers = omap4_dm_timers;
+                dm_source_names = omap4_dm_source_names;
+                dm_source_clocks = omap4_dm_source_clocks;
         }
 
         if (cpu_class_is_omap2())
@@ -723,7 +775,8 @@ int __init omap_dm_timer_init(void)
         for (i = 0; i < dm_timer_count; i++) {
                 timer = &dm_timers[i];
                 timer->io_base = IO_ADDRESS(timer->phys_base);
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
+                                        defined(CONFIG_ARCH_OMAP4)
                 if (cpu_class_is_omap2()) {
                         char clk_name[16];
                         sprintf(clk_name, "gpt%d_ick", i + 1);