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authorJanusz Krzysztofik <jkrzyszt@tis.icnet.pl>2009-12-11 19:16:33 -0500
committerTony Lindgren <tony@atomide.com>2009-12-11 19:16:33 -0500
commitf8e9e98454606e43b728269de21db349f57861c7 (patch)
treecc38265982b60e93f5271ca7578e00161046c30e /arch/arm/plat-omap/dma.c
parent414f552ad872e19a7471644317a60f3cbba25ced (diff)
omap1: DMA: move LCD related code from plat-omap to mach-omap1
All of the LCD DMA code in plat-omap/dma.c appears to be OMAP1-only (and apparently only is available on a subset of OMAP1 chips). Move this code to mach-omap1/lcd_dma.c. Tested on OMAP1510 Amstrad Delta. Compile-tested with omap_generic_2420_defconfig. Reported-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl> Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/plat-omap/dma.c')
-rw-r--r--arch/arm/plat-omap/dma.c410
1 files changed, 2 insertions, 408 deletions
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index d17375e06a1e..09d82b3c66ce 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -47,7 +47,6 @@ enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
47#endif 47#endif
48 48
49#define OMAP_DMA_ACTIVE 0x01 49#define OMAP_DMA_ACTIVE 0x01
50#define OMAP_DMA_CCR_EN (1 << 7)
51#define OMAP2_DMA_CSR_CLEAR_MASK 0xffe 50#define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
52 51
53#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec) 52#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
@@ -1120,17 +1119,8 @@ int omap_dma_running(void)
1120{ 1119{
1121 int lch; 1120 int lch;
1122 1121
1123 /* 1122 if (cpu_class_is_omap1())
1124 * On OMAP1510, internal LCD controller will start the transfer 1123 if (omap_lcd_dma_running())
1125 * when it gets enabled, so assume DMA running if LCD enabled.
1126 */
1127 if (cpu_is_omap1510())
1128 if (omap_readw(0xfffec000 + 0x00) & (1 << 0))
1129 return 1;
1130
1131 /* Check if LCD DMA is running */
1132 if (cpu_is_omap16xx())
1133 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
1134 return 1; 1124 return 1;
1135 1125
1136 for (lch = 0; lch < dma_chan_count; lch++) 1126 for (lch = 0; lch < dma_chan_count; lch++)
@@ -1990,377 +1980,6 @@ static struct irqaction omap24xx_dma_irq;
1990 1980
1991/*----------------------------------------------------------------------------*/ 1981/*----------------------------------------------------------------------------*/
1992 1982
1993static struct lcd_dma_info {
1994 spinlock_t lock;
1995 int reserved;
1996 void (*callback)(u16 status, void *data);
1997 void *cb_data;
1998
1999 int active;
2000 unsigned long addr, size;
2001 int rotate, data_type, xres, yres;
2002 int vxres;
2003 int mirror;
2004 int xscale, yscale;
2005 int ext_ctrl;
2006 int src_port;
2007 int single_transfer;
2008} lcd_dma;
2009
2010void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
2011 int data_type)
2012{
2013 lcd_dma.addr = addr;
2014 lcd_dma.data_type = data_type;
2015 lcd_dma.xres = fb_xres;
2016 lcd_dma.yres = fb_yres;
2017}
2018EXPORT_SYMBOL(omap_set_lcd_dma_b1);
2019
2020void omap_set_lcd_dma_src_port(int port)
2021{
2022 lcd_dma.src_port = port;
2023}
2024
2025void omap_set_lcd_dma_ext_controller(int external)
2026{
2027 lcd_dma.ext_ctrl = external;
2028}
2029EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
2030
2031void omap_set_lcd_dma_single_transfer(int single)
2032{
2033 lcd_dma.single_transfer = single;
2034}
2035EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
2036
2037void omap_set_lcd_dma_b1_rotation(int rotate)
2038{
2039 if (omap_dma_in_1510_mode()) {
2040 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
2041 BUG();
2042 return;
2043 }
2044 lcd_dma.rotate = rotate;
2045}
2046EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
2047
2048void omap_set_lcd_dma_b1_mirror(int mirror)
2049{
2050 if (omap_dma_in_1510_mode()) {
2051 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
2052 BUG();
2053 }
2054 lcd_dma.mirror = mirror;
2055}
2056EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
2057
2058void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
2059{
2060 if (omap_dma_in_1510_mode()) {
2061 printk(KERN_ERR "DMA virtual resulotion is not supported "
2062 "in 1510 mode\n");
2063 BUG();
2064 }
2065 lcd_dma.vxres = vxres;
2066}
2067EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
2068
2069void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
2070{
2071 if (omap_dma_in_1510_mode()) {
2072 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
2073 BUG();
2074 }
2075 lcd_dma.xscale = xscale;
2076 lcd_dma.yscale = yscale;
2077}
2078EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
2079
2080static void set_b1_regs(void)
2081{
2082 unsigned long top, bottom;
2083 int es;
2084 u16 w;
2085 unsigned long en, fn;
2086 long ei, fi;
2087 unsigned long vxres;
2088 unsigned int xscale, yscale;
2089
2090 switch (lcd_dma.data_type) {
2091 case OMAP_DMA_DATA_TYPE_S8:
2092 es = 1;
2093 break;
2094 case OMAP_DMA_DATA_TYPE_S16:
2095 es = 2;
2096 break;
2097 case OMAP_DMA_DATA_TYPE_S32:
2098 es = 4;
2099 break;
2100 default:
2101 BUG();
2102 return;
2103 }
2104
2105 vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
2106 xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
2107 yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
2108 BUG_ON(vxres < lcd_dma.xres);
2109
2110#define PIXADDR(x, y) (lcd_dma.addr + \
2111 ((y) * vxres * yscale + (x) * xscale) * es)
2112#define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
2113
2114 switch (lcd_dma.rotate) {
2115 case 0:
2116 if (!lcd_dma.mirror) {
2117 top = PIXADDR(0, 0);
2118 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2119 /* 1510 DMA requires the bottom address to be 2 more
2120 * than the actual last memory access location. */
2121 if (omap_dma_in_1510_mode() &&
2122 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
2123 bottom += 2;
2124 ei = PIXSTEP(0, 0, 1, 0);
2125 fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
2126 } else {
2127 top = PIXADDR(lcd_dma.xres - 1, 0);
2128 bottom = PIXADDR(0, lcd_dma.yres - 1);
2129 ei = PIXSTEP(1, 0, 0, 0);
2130 fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
2131 }
2132 en = lcd_dma.xres;
2133 fn = lcd_dma.yres;
2134 break;
2135 case 90:
2136 if (!lcd_dma.mirror) {
2137 top = PIXADDR(0, lcd_dma.yres - 1);
2138 bottom = PIXADDR(lcd_dma.xres - 1, 0);
2139 ei = PIXSTEP(0, 1, 0, 0);
2140 fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
2141 } else {
2142 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2143 bottom = PIXADDR(0, 0);
2144 ei = PIXSTEP(0, 1, 0, 0);
2145 fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
2146 }
2147 en = lcd_dma.yres;
2148 fn = lcd_dma.xres;
2149 break;
2150 case 180:
2151 if (!lcd_dma.mirror) {
2152 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2153 bottom = PIXADDR(0, 0);
2154 ei = PIXSTEP(1, 0, 0, 0);
2155 fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
2156 } else {
2157 top = PIXADDR(0, lcd_dma.yres - 1);
2158 bottom = PIXADDR(lcd_dma.xres - 1, 0);
2159 ei = PIXSTEP(0, 0, 1, 0);
2160 fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
2161 }
2162 en = lcd_dma.xres;
2163 fn = lcd_dma.yres;
2164 break;
2165 case 270:
2166 if (!lcd_dma.mirror) {
2167 top = PIXADDR(lcd_dma.xres - 1, 0);
2168 bottom = PIXADDR(0, lcd_dma.yres - 1);
2169 ei = PIXSTEP(0, 0, 0, 1);
2170 fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
2171 } else {
2172 top = PIXADDR(0, 0);
2173 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2174 ei = PIXSTEP(0, 0, 0, 1);
2175 fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
2176 }
2177 en = lcd_dma.yres;
2178 fn = lcd_dma.xres;
2179 break;
2180 default:
2181 BUG();
2182 return; /* Suppress warning about uninitialized vars */
2183 }
2184
2185 if (omap_dma_in_1510_mode()) {
2186 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
2187 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
2188 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
2189 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
2190
2191 return;
2192 }
2193
2194 /* 1610 regs */
2195 omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
2196 omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
2197 omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
2198 omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
2199
2200 omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
2201 omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
2202
2203 w = omap_readw(OMAP1610_DMA_LCD_CSDP);
2204 w &= ~0x03;
2205 w |= lcd_dma.data_type;
2206 omap_writew(w, OMAP1610_DMA_LCD_CSDP);
2207
2208 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2209 /* Always set the source port as SDRAM for now*/
2210 w &= ~(0x03 << 6);
2211 if (lcd_dma.callback != NULL)
2212 w |= 1 << 1; /* Block interrupt enable */
2213 else
2214 w &= ~(1 << 1);
2215 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2216
2217 if (!(lcd_dma.rotate || lcd_dma.mirror ||
2218 lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
2219 return;
2220
2221 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2222 /* Set the double-indexed addressing mode */
2223 w |= (0x03 << 12);
2224 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2225
2226 omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
2227 omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
2228 omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
2229}
2230
2231static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
2232{
2233 u16 w;
2234
2235 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2236 if (unlikely(!(w & (1 << 3)))) {
2237 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
2238 return IRQ_NONE;
2239 }
2240 /* Ack the IRQ */
2241 w |= (1 << 3);
2242 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2243 lcd_dma.active = 0;
2244 if (lcd_dma.callback != NULL)
2245 lcd_dma.callback(w, lcd_dma.cb_data);
2246
2247 return IRQ_HANDLED;
2248}
2249
2250int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
2251 void *data)
2252{
2253 spin_lock_irq(&lcd_dma.lock);
2254 if (lcd_dma.reserved) {
2255 spin_unlock_irq(&lcd_dma.lock);
2256 printk(KERN_ERR "LCD DMA channel already reserved\n");
2257 BUG();
2258 return -EBUSY;
2259 }
2260 lcd_dma.reserved = 1;
2261 spin_unlock_irq(&lcd_dma.lock);
2262 lcd_dma.callback = callback;
2263 lcd_dma.cb_data = data;
2264 lcd_dma.active = 0;
2265 lcd_dma.single_transfer = 0;
2266 lcd_dma.rotate = 0;
2267 lcd_dma.vxres = 0;
2268 lcd_dma.mirror = 0;
2269 lcd_dma.xscale = 0;
2270 lcd_dma.yscale = 0;
2271 lcd_dma.ext_ctrl = 0;
2272 lcd_dma.src_port = 0;
2273
2274 return 0;
2275}
2276EXPORT_SYMBOL(omap_request_lcd_dma);
2277
2278void omap_free_lcd_dma(void)
2279{
2280 spin_lock(&lcd_dma.lock);
2281 if (!lcd_dma.reserved) {
2282 spin_unlock(&lcd_dma.lock);
2283 printk(KERN_ERR "LCD DMA is not reserved\n");
2284 BUG();
2285 return;
2286 }
2287 if (!enable_1510_mode)
2288 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
2289 OMAP1610_DMA_LCD_CCR);
2290 lcd_dma.reserved = 0;
2291 spin_unlock(&lcd_dma.lock);
2292}
2293EXPORT_SYMBOL(omap_free_lcd_dma);
2294
2295void omap_enable_lcd_dma(void)
2296{
2297 u16 w;
2298
2299 /*
2300 * Set the Enable bit only if an external controller is
2301 * connected. Otherwise the OMAP internal controller will
2302 * start the transfer when it gets enabled.
2303 */
2304 if (enable_1510_mode || !lcd_dma.ext_ctrl)
2305 return;
2306
2307 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2308 w |= 1 << 8;
2309 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2310
2311 lcd_dma.active = 1;
2312
2313 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2314 w |= 1 << 7;
2315 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2316}
2317EXPORT_SYMBOL(omap_enable_lcd_dma);
2318
2319void omap_setup_lcd_dma(void)
2320{
2321 BUG_ON(lcd_dma.active);
2322 if (!enable_1510_mode) {
2323 /* Set some reasonable defaults */
2324 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
2325 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
2326 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
2327 }
2328 set_b1_regs();
2329 if (!enable_1510_mode) {
2330 u16 w;
2331
2332 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2333 /*
2334 * If DMA was already active set the end_prog bit to have
2335 * the programmed register set loaded into the active
2336 * register set.
2337 */
2338 w |= 1 << 11; /* End_prog */
2339 if (!lcd_dma.single_transfer)
2340 w |= (3 << 8); /* Auto_init, repeat */
2341 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2342 }
2343}
2344EXPORT_SYMBOL(omap_setup_lcd_dma);
2345
2346void omap_stop_lcd_dma(void)
2347{
2348 u16 w;
2349
2350 lcd_dma.active = 0;
2351 if (enable_1510_mode || !lcd_dma.ext_ctrl)
2352 return;
2353
2354 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2355 w &= ~(1 << 7);
2356 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2357
2358 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2359 w &= ~(1 << 8);
2360 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2361}
2362EXPORT_SYMBOL(omap_stop_lcd_dma);
2363
2364void omap_dma_global_context_save(void) 1983void omap_dma_global_context_save(void)
2365{ 1984{
2366 omap_dma_global_context.dma_irqenable_l0 = 1985 omap_dma_global_context.dma_irqenable_l0 =
@@ -2465,14 +2084,6 @@ static int __init omap_init_dma(void)
2465 dma_chan_count = 16; 2084 dma_chan_count = 16;
2466 } else 2085 } else
2467 dma_chan_count = 9; 2086 dma_chan_count = 9;
2468 if (cpu_is_omap16xx()) {
2469 u16 w;
2470
2471 /* this would prevent OMAP sleep */
2472 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2473 w &= ~(1 << 8);
2474 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2475 }
2476 } else if (cpu_class_is_omap2()) { 2087 } else if (cpu_class_is_omap2()) {
2477 u8 revision = dma_read(REVISION) & 0xff; 2088 u8 revision = dma_read(REVISION) & 0xff;
2478 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n", 2089 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
@@ -2483,7 +2094,6 @@ static int __init omap_init_dma(void)
2483 return 0; 2094 return 0;
2484 } 2095 }
2485 2096
2486 spin_lock_init(&lcd_dma.lock);
2487 spin_lock_init(&dma_chan_lock); 2097 spin_lock_init(&dma_chan_lock);
2488 2098
2489 for (ch = 0; ch < dma_chan_count; ch++) { 2099 for (ch = 0; ch < dma_chan_count; ch++) {
@@ -2548,22 +2158,6 @@ static int __init omap_init_dma(void)
2548 } 2158 }
2549 } 2159 }
2550 2160
2551
2552 /* FIXME: Update LCD DMA to work on 24xx */
2553 if (cpu_class_is_omap1()) {
2554 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
2555 "LCD DMA", NULL);
2556 if (r != 0) {
2557 int i;
2558
2559 printk(KERN_ERR "unable to request IRQ for LCD DMA "
2560 "(error %d)\n", r);
2561 for (i = 0; i < dma_chan_count; i++)
2562 free_irq(omap1_dma_irq[i], (void *) (i + 1));
2563 goto out_free;
2564 }
2565 }
2566
2567 return 0; 2161 return 0;
2568 2162
2569out_free: 2163out_free: