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authorPeter Ujfalusi <peter.ujfalusi@ti.com>2011-12-09 16:38:00 -0500
committerTony Lindgren <tony@atomide.com>2011-12-09 16:38:00 -0500
commit06e8077b556a372871c04dd68f47e8c25e9ca348 (patch)
treeb792a9ad2ef20d6e837c6b1749ef817c6286b44e /arch/arm/plat-omap/dma.c
parent7ba966804f58ccd81375827a71222efaa131aa70 (diff)
ARM: OMAP2+: DMA: Workaround for invalid destination position
If the DMA destination position has been asked before the first actual data transfer has been done, the CDAC register still contains 0 (it is initialized to 0 at omsp_dma_start). If CDAC == 0, return the programmed start address. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Reviewed-by: Jarkko Nikula <jarkko.nikula@bitmer.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/plat-omap/dma.c')
-rw-r--r--arch/arm/plat-omap/dma.c10
1 files changed, 9 insertions, 1 deletions
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index a9983b695a18..002fb4d96bbc 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -1074,8 +1074,16 @@ dma_addr_t omap_get_dma_dst_pos(int lch)
1074 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is 1074 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1075 * read before the DMA controller finished disabling the channel. 1075 * read before the DMA controller finished disabling the channel.
1076 */ 1076 */
1077 if (!cpu_is_omap15xx() && offset == 0) 1077 if (!cpu_is_omap15xx() && offset == 0) {
1078 offset = p->dma_read(CDAC, lch); 1078 offset = p->dma_read(CDAC, lch);
1079 /*
1080 * CDAC == 0 indicates that the DMA transfer on the channel has
1081 * not been started (no data has been transferred so far).
1082 * Return the programmed destination start address in this case.
1083 */
1084 if (unlikely(!offset))
1085 offset = p->dma_read(CDSA, lch);
1086 }
1079 1087
1080 if (cpu_class_is_omap1()) 1088 if (cpu_class_is_omap1())
1081 offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000); 1089 offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);