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authorDavid S. Miller <davem@sunset.davemloft.net>2006-02-08 05:53:50 -0500
committerDavid S. Miller <davem@sunset.davemloft.net>2006-03-20 04:12:01 -0500
commit5b0c0572fcd6204675c5f7ddfa572b5017f817dd (patch)
tree1075a61338e887bd6d4ecd4517646ef95dc09fbc /arch/arm/plat-omap/devices.c
parentac29c11d4cd4fa1fac968e99998a956405732f2f (diff)
[SPARC64]: Sun4v interrupt handling.
Sun4v has 4 interrupt queues: cpu, device, resumable errors, and non-resumable errors. A set of head/tail offset pointers help maintain a work queue in physical memory. The entries are 64-bytes in size. Each queue is allocated then registered with the hypervisor as we bring cpus up. The two error queues each get a kernel side buffer that we use to quickly empty the main interrupt queue before we call up to C code to log the event and possibly take evasive action. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/arm/plat-omap/devices.c')
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