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authorArnaud Patard (Rtp) <arnaud.patard@rtp-net.org>2010-12-20 10:48:57 -0500
committerSascha Hauer <s.hauer@pengutronix.de>2011-01-03 04:20:23 -0500
commit8305ed75d1418f02933a48bcabdbb5032d885628 (patch)
tree2708abad21787d76a2ea838c56ddc9d167c4a7a6 /arch/arm/plat-mxc
parent08406f540c7ce4cfed96fb240906eee04b9e3eb7 (diff)
MX51: Add support for usb host 2
Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/plat-mxc')
-rw-r--r--arch/arm/plat-mxc/ehci.c25
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc_ehci.h1
2 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c
index a45660301b08..8772ce346a58 100644
--- a/arch/arm/plat-mxc/ehci.c
+++ b/arch/arm/plat-mxc/ehci.c
@@ -49,6 +49,7 @@
49 49
50#define MXC_OTG_OFFSET 0 50#define MXC_OTG_OFFSET 0
51#define MXC_H1_OFFSET 0x200 51#define MXC_H1_OFFSET 0x200
52#define MXC_H2_OFFSET 0x400
52 53
53/* USB_CTRL */ 54/* USB_CTRL */
54#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */ 55#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */
@@ -61,6 +62,11 @@
61#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */ 62#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
62#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */ 63#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */
63 64
65/* USBH2CTRL */
66#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
67#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
68#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
69
64#define MXC_USBCMD_OFFSET 0x140 70#define MXC_USBCMD_OFFSET 0x140
65 71
66/* USBCMD */ 72/* USBCMD */
@@ -266,6 +272,9 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
266 case 1: /* Host 1 port */ 272 case 1: /* Host 1 port */
267 usbotg_base = usb_base + MXC_H1_OFFSET; 273 usbotg_base = usb_base + MXC_H1_OFFSET;
268 break; 274 break;
275 case 2: /* Host 2 port */
276 usbotg_base = usb_base + MXC_H2_OFFSET;
277 break;
269 default: 278 default:
270 printk(KERN_ERR"%s no such port %d\n", __func__, port); 279 printk(KERN_ERR"%s no such port %d\n", __func__, port);
271 ret = -ENOENT; 280 ret = -ENOENT;
@@ -329,6 +338,22 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
329 v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK; 338 v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
330 __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET); 339 __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
331 break; 340 break;
341 case 2: /* Host 2 ULPI */
342 v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
343 if (flags & MXC_EHCI_WAKEUP_ENABLED) {
344 /* HOST1 wakeup/ULPI intr enable */
345 v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
346 } else {
347 /* HOST1 wakeup/ULPI intr disable */
348 v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
349 }
350
351 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
352 v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
353 else
354 v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
355 __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
356 break;
332 } 357 }
333 358
334error: 359error:
diff --git a/arch/arm/plat-mxc/include/mach/mxc_ehci.h b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
index 7fc5f9946199..a523a4079299 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_ehci.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
@@ -31,6 +31,7 @@
31#define MXC_USBCTRL_OFFSET 0 31#define MXC_USBCTRL_OFFSET 0
32#define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8 32#define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8
33#define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc 33#define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc
34#define MXC_USBH2CTRL_OFFSET 0x14
34 35
35#define MX5_USBOTHER_REGS_OFFSET 0x800 36#define MX5_USBOTHER_REGS_OFFSET 0x800
36 37