Merge branch 'next/soc' of git://git.linaro.org/people/arnd/arm-soc

* 'next/soc' of git://git.linaro.org/people/arnd/arm-soc: (21 commits)
  MAINTAINERS: add ARM/FREESCALE IMX6 entry
  arm/imx: merge i.MX3 and i.MX6
  arm/imx6q: add suspend/resume support
  arm/imx6q: add device tree machine support
  arm/imx6q: add smp and cpu hotplug support
  arm/imx6q: add core drivers clock, gpc, mmdc and src
  arm/imx: add gic_handle_irq function
  arm/imx6q: add core definitions and low-level debug uart
  arm/imx6q: add device tree source
  ARM: highbank: add suspend support
  ARM: highbank: Add cpu hotplug support
  ARM: highbank: add SMP support
  MAINTAINERS: add Calxeda Highbank ARM platform
  ARM: add Highbank core platform support
  ARM: highbank: add devicetree source
  ARM: l2x0: add empty l2x0_of_init
  picoxcell: add a definition of VMALLOC_END
  picoxcell: remove custom ioremap implementation
  picoxcell: add the DTS for the PC7302 board
  picoxcell: add the DTS for pc3x2 and pc3x3 devices
  ...

Fix up trivial conflicts in arch/arm/Kconfig, and some more header file
conflicts in arch/arm/mach-omap2/board-generic.c (as per an ealier merge
by Arnd).

9 files changed, 140 insertions, 7 deletions

diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 4bdc975581eb..a08a95107a63 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -6,7 +6,7 @@ menu "Freescale MXC Implementations"
 
 choice
         prompt "Freescale CPU family:"
-        default ARCH_MX3
+        default ARCH_IMX_V6_V7
 
 config ARCH_IMX_V4_V5
         bool "i.MX1, i.MX21, i.MX25, i.MX27"
@@ -16,10 +16,13 @@ config ARCH_IMX_V4_V5
           This enables support for systems based on the Freescale i.MX ARMv4
           and ARMv5 SoCs
 
-config ARCH_MX3
-        bool "MX3-based"
+config ARCH_IMX_V6_V7
+        bool "i.MX3, i.MX6"
+        select AUTO_ZRELADDR if !ZBOOT_ROM
+        select ARM_PATCH_PHYS_VIRT
         help
-          This enables support for systems based on the Freescale i.MX3 family
+          This enables support for systems based on the Freescale i.MX3 and i.MX6
+          family.
 
 config ARCH_MX5
         bool "i.MX50, i.MX51, i.MX53"
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index d53c35fe2ea7..b9f0f5f499a4 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -5,7 +5,7 @@
 # Common support
 obj-y := clock.o time.o devices.o cpu.o system.o irq-common.o
 
-# MX51 uses the TZIC interrupt controller, older platforms use AVIC
+obj-$(CONFIG_ARM_GIC) += gic.o
 obj-$(CONFIG_MXC_TZIC) += tzic.o
 obj-$(CONFIG_MXC_AVIC) += avic.o
 
diff --git a/arch/arm/plat-mxc/gic.c b/arch/arm/plat-mxc/gic.c
new file mode 100644
index 000000000000..b3b8eed263b8
--- /dev/null
+++ b/arch/arm/plat-mxc/gic.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/io.h>
+#include <asm/exception.h>
+#include <asm/localtimer.h>
+#include <asm/hardware/gic.h>
+#ifdef CONFIG_SMP
+#include <asm/smp.h>
+#endif
+
+asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
+{
+        u32 irqstat, irqnr;
+
+        do {
+                irqstat = readl_relaxed(gic_cpu_base_addr + GIC_CPU_INTACK);
+                irqnr = irqstat & 0x3ff;
+                if (irqnr == 1023)
+                        break;
+
+                if (irqnr > 29 && irqnr < 1021)
+                        handle_IRQ(irqnr, regs);
+#ifdef CONFIG_SMP
+                else if (irqnr < 16) {
+                        writel_relaxed(irqstat, gic_cpu_base_addr +
+                                                GIC_CPU_EOI);
+                        handle_IPI(irqnr, regs);
+                }
+#endif
+#ifdef CONFIG_LOCAL_TIMERS
+                else if (irqnr == 29) {
+                        writel_relaxed(irqstat, gic_cpu_base_addr +
+                                                GIC_CPU_EOI);
+                        handle_local_timer(regs);
+                }
+#endif
+        } while (1);
+}
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index c850af3650ea..83b745a5e1b7 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -13,6 +13,7 @@
 
 struct platform_device;
 struct clk;
+enum mxc_cpu_pwr_mode;
 
 extern void mx1_map_io(void);
 extern void mx21_map_io(void);
@@ -66,6 +67,7 @@ extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
                         unsigned long ckih1, unsigned long ckih2);
 extern int mx51_clocks_init_dt(void);
 extern int mx53_clocks_init_dt(void);
+extern int mx6q_clocks_init(void);
 extern struct platform_device *mxc_register_gpio(char *name, int id,
         resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
 extern void mxc_set_cpu_type(unsigned int type);
@@ -88,6 +90,7 @@ extern void imx_print_silicon_rev(const char *cpu, int srev);
 
 void avic_handle_irq(struct pt_regs *);
 void tzic_handle_irq(struct pt_regs *);
+void gic_handle_irq(struct pt_regs *);
 
 #define imx1_handle_irq avic_handle_irq
 #define imx21_handle_irq avic_handle_irq
@@ -98,10 +101,36 @@ void tzic_handle_irq(struct pt_regs *);
 #define imx50_handle_irq tzic_handle_irq
 #define imx51_handle_irq tzic_handle_irq
 #define imx53_handle_irq tzic_handle_irq
+#define imx6q_handle_irq gic_handle_irq
 
+extern void imx_enable_cpu(int cpu, bool enable);
+extern void imx_set_cpu_jump(int cpu, void *jump_addr);
+#ifdef CONFIG_DEBUG_LL
+extern void imx_lluart_map_io(void);
+#else
+static inline void imx_lluart_map_io(void) {}
+#endif
+extern void v7_cpu_resume(void);
+extern u32 *pl310_get_save_ptr(void);
+#ifdef CONFIG_SMP
+extern void v7_secondary_startup(void);
+extern void imx_scu_map_io(void);
+extern void imx_smp_prepare(void);
+#else
+static inline void imx_scu_map_io(void) {}
+static inline void imx_smp_prepare(void) {}
+#endif
+extern void imx_enable_cpu(int cpu, bool enable);
+extern void imx_set_cpu_jump(int cpu, void *jump_addr);
+extern void imx_src_init(void);
+extern void imx_gpc_init(void);
+extern void imx_gpc_pre_suspend(void);
+extern void imx_gpc_post_resume(void);
 extern void imx51_babbage_common_init(void);
 extern void imx53_ard_common_init(void);
 extern void imx53_evk_common_init(void);
 extern void imx53_qsb_common_init(void);
 extern void imx53_smd_common_init(void);
+extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
+extern void imx6q_pm_init(void);
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index 72986013c1fb..6e192c4a391a 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -24,6 +24,8 @@
 #define UART_PADDR      MX51_UART1_BASE_ADDR
 #elif defined (CONFIG_DEBUG_IMX50_IMX53_UART)
 #define UART_PADDR      MX53_UART1_BASE_ADDR
+#elif defined (CONFIG_DEBUG_IMX6Q_UART)
+#define UART_PADDR      MX6Q_UART4_BASE_ADDR
 #endif
 
 #define UART_VADDR      IMX_IO_ADDRESS(UART_PADDR)
diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S
index 842fbcb0d6cc..9fe0dfcf4e7e 100644
--- a/arch/arm/plat-mxc/include/mach/entry-macro.S
+++ b/arch/arm/plat-mxc/include/mach/entry-macro.S
@@ -22,3 +22,9 @@
 
         .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
         .endm
+
+        .macro test_for_ipi, irqnr, irqstat, base, tmp
+        .endm
+
+        .macro test_for_ltirq, irqnr, irqstat, base, tmp
+        .endm
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index eba3118adfbb..a599f01f8b92 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -91,6 +91,11 @@
  *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
  *      AIPS1   0x53f00000+0x100000     ->      0xf5700000+0x100000
  *      AIPS2   0x63f00000+0x100000     ->      0xf5300000+0x100000
+ * mx6q:
+ *      SCU     0x00a00000+0x001000     ->      0xf4000000+0x001000
+ *      CCM     0x020c4000+0x004000     ->      0xf42c4000+0x004000
+ *      ANATOP  0x020c8000+0x001000     ->      0xf42c8000+0x001000
+ *      UART4   0x021f0000+0x004000     ->      0xf42f0000+0x004000
  */
 #define IMX_IO_P2V(x)   (                                               \
                         0xf4000000 +                                    \
@@ -102,6 +107,7 @@
 
 #include <mach/mxc.h>
 
+#include <mach/mx6q.h>
 #include <mach/mx50.h>
 #include <mach/mx51.h>
 #include <mach/mx53.h>
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index 00e812bbd81d..fd9efb044656 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -14,9 +14,15 @@
 #include <asm-generic/gpio.h>
 
 /*
- * SoCs with TZIC interrupt controller have 128 IRQs, those with AVIC have 64
+ * SoCs with GIC interrupt controller have 160 IRQs, those with TZIC
+ * have 128 IRQs, and those with AVIC have 64.
+ *
+ * To support single image, the biggest number should be defined on
+ * top of the list.
  */
-#ifdef CONFIG_MXC_TZIC
+#if defined CONFIG_ARM_GIC
+#define MXC_INTERNAL_IRQS       160
+#elif defined CONFIG_MXC_TZIC
 #define MXC_INTERNAL_IRQS       128
 #else
 #define MXC_INTERNAL_IRQS       64
diff --git a/arch/arm/plat-mxc/include/mach/mx6q.h b/arch/arm/plat-mxc/include/mach/mx6q.h
new file mode 100644
index 000000000000..254a561a2799
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx6q.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __MACH_MX6Q_H__
+#define __MACH_MX6Q_H__
+
+#define MX6Q_IO_P2V(x)                  IMX_IO_P2V(x)
+#define MX6Q_IO_ADDRESS(x)              IOMEM(MX6Q_IO_P2V(x))
+
+/*
+ * The following are the blocks that need to be statically mapped.
+ * For other blocks, the base address really should be retrieved from
+ * device tree.
+ */
+#define MX6Q_SCU_BASE_ADDR              0x00a00000
+#define MX6Q_SCU_SIZE                   0x1000
+#define MX6Q_CCM_BASE_ADDR              0x020c4000
+#define MX6Q_CCM_SIZE                   0x4000
+#define MX6Q_ANATOP_BASE_ADDR           0x020c8000
+#define MX6Q_ANATOP_SIZE                0x1000
+#define MX6Q_UART4_BASE_ADDR            0x021f0000
+#define MX6Q_UART4_SIZE                 0x4000
+
+#endif  /* __MACH_MX6Q_H__ */