Merge branch 'for-rmk' of git://pasiphae.extern.pengutronix.de/git/imx/linux-2.6.git

Merge branch 'imx-devel' into devel

16 files changed, 1071 insertions, 16 deletions

diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index e14eaad11dd5..b2a7e3fad117 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -23,4 +23,15 @@ source "arch/arm/mach-mx3/Kconfig"
 
 endmenu
 
+config MXC_IRQ_PRIOR
+        bool "Use IRQ priority"
+        depends on ARCH_MXC
+        help
+          Select this if you want to use prioritized IRQ handling.
+          This feature prevents higher priority ISR to be interrupted
+          by lower priority IRQ even IRQF_DISABLED flag is not set.
+          This may be useful in embedded applications, where are strong
+          requirements for timing.
+          Say N here, unless you have a specialized requirement.
+
 endif
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index db66e9ae8414..067556f7c91f 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -3,6 +3,6 @@
 #
 
 # Common support
-obj-y := irq.o clock.o gpio.o time.o
+obj-y := irq.o clock.o gpio.o time.o devices.o
 
-obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o
+obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o
diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c
new file mode 100644
index 000000000000..c66748267c45
--- /dev/null
+++ b/arch/arm/plat-mxc/devices.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+
+int __init mxc_register_device(struct platform_device *pdev, void *data)
+{
+        int ret;
+
+        pdev->dev.platform_data = data;
+
+        ret = platform_device_register(pdev);
+        if (ret)
+                pr_debug("Unable to register platform device '%s': %d\n",
+                         pdev->name, ret);
+
+        return ret;
+}
+
diff --git a/arch/arm/plat-mxc/dma-mx1-mx2.c b/arch/arm/plat-mxc/dma-mx1-mx2.c
new file mode 100644
index 000000000000..b296f19fd89a
--- /dev/null
+++ b/arch/arm/plat-mxc/dma-mx1-mx2.c
@@ -0,0 +1,840 @@
+/*
+ *  linux/arch/arm/plat-mxc/dma-mx1-mx2.c
+ *
+ *  i.MX DMA registration and IRQ dispatching
+ *
+ * Copyright 2006 Pavel Pisa <pisa@cmp.felk.cvut.cz>
+ * Copyright 2008 Juergen Beisert, <kernel@pengutronix.de>
+ * Copyright 2008 Sascha Hauer, <s.hauer@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/scatterlist.h>
+#include <linux/io.h>
+
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <mach/hardware.h>
+#include <asm/dma.h>
+#include <mach/dma-mx1-mx2.h>
+
+#define DMA_DCR     0x00                /* Control Register */
+#define DMA_DISR    0x04                /* Interrupt status Register */
+#define DMA_DIMR    0x08                /* Interrupt mask Register */
+#define DMA_DBTOSR  0x0c                /* Burst timeout status Register */
+#define DMA_DRTOSR  0x10                /* Request timeout Register */
+#define DMA_DSESR   0x14                /* Transfer Error Status Register */
+#define DMA_DBOSR   0x18                /* Buffer overflow status Register */
+#define DMA_DBTOCR  0x1c                /* Burst timeout control Register */
+#define DMA_WSRA    0x40                /* W-Size Register A */
+#define DMA_XSRA    0x44                /* X-Size Register A */
+#define DMA_YSRA    0x48                /* Y-Size Register A */
+#define DMA_WSRB    0x4c                /* W-Size Register B */
+#define DMA_XSRB    0x50                /* X-Size Register B */
+#define DMA_YSRB    0x54                /* Y-Size Register B */
+#define DMA_SAR(x)  (0x80 + ((x) << 6)) /* Source Address Registers */
+#define DMA_DAR(x)  (0x84 + ((x) << 6)) /* Destination Address Registers */
+#define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
+#define DMA_CCR(x)  (0x8c + ((x) << 6)) /* Control Registers */
+#define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
+#define DMA_BLR(x)  (0x94 + ((x) << 6)) /* Burst length Registers */
+#define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
+#define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
+#define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
+
+#define DCR_DRST           (1<<1)
+#define DCR_DEN            (1<<0)
+#define DBTOCR_EN          (1<<15)
+#define DBTOCR_CNT(x)      ((x) & 0x7fff)
+#define CNTR_CNT(x)        ((x) & 0xffffff)
+#define CCR_ACRPT          (1<<14)
+#define CCR_DMOD_LINEAR    (0x0 << 12)
+#define CCR_DMOD_2D        (0x1 << 12)
+#define CCR_DMOD_FIFO      (0x2 << 12)
+#define CCR_DMOD_EOBFIFO   (0x3 << 12)
+#define CCR_SMOD_LINEAR    (0x0 << 10)
+#define CCR_SMOD_2D        (0x1 << 10)
+#define CCR_SMOD_FIFO      (0x2 << 10)
+#define CCR_SMOD_EOBFIFO   (0x3 << 10)
+#define CCR_MDIR_DEC       (1<<9)
+#define CCR_MSEL_B         (1<<8)
+#define CCR_DSIZ_32        (0x0 << 6)
+#define CCR_DSIZ_8         (0x1 << 6)
+#define CCR_DSIZ_16        (0x2 << 6)
+#define CCR_SSIZ_32        (0x0 << 4)
+#define CCR_SSIZ_8         (0x1 << 4)
+#define CCR_SSIZ_16        (0x2 << 4)
+#define CCR_REN            (1<<3)
+#define CCR_RPT            (1<<2)
+#define CCR_FRC            (1<<1)
+#define CCR_CEN            (1<<0)
+#define RTOR_EN            (1<<15)
+#define RTOR_CLK           (1<<14)
+#define RTOR_PSC           (1<<13)
+
+/*
+ * struct imx_dma_channel - i.MX specific DMA extension
+ * @name: name specified by DMA client
+ * @irq_handler: client callback for end of transfer
+ * @err_handler: client callback for error condition
+ * @data: clients context data for callbacks
+ * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
+ * @sg: pointer to the actual read/written chunk for scatter-gather emulation
+ * @resbytes: total residual number of bytes to transfer
+ *            (it can be lower or same as sum of SG mapped chunk sizes)
+ * @sgcount: number of chunks to be read/written
+ *
+ * Structure is used for IMX DMA processing. It would be probably good
+ * @struct dma_struct in the future for external interfacing and use
+ * @struct imx_dma_channel only as extension to it.
+ */
+
+struct imx_dma_channel {
+        const char *name;
+        void (*irq_handler) (int, void *);
+        void (*err_handler) (int, void *, int errcode);
+        void (*prog_handler) (int, void *, struct scatterlist *);
+        void *data;
+        dmamode_t  dma_mode;
+        struct scatterlist *sg;
+        unsigned int resbytes;
+        int dma_num;
+
+        int in_use;
+
+        u32 ccr_from_device;
+        u32 ccr_to_device;
+
+        struct timer_list watchdog;
+
+        int hw_chaining;
+};
+
+static struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS];
+
+static struct clk *dma_clk;
+
+static int imx_dma_hw_chain(struct imx_dma_channel *imxdma)
+{
+        if (cpu_is_mx27())
+                return imxdma->hw_chaining;
+        else
+                return 0;
+}
+
+
+/*
+ * imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation
+ */
+static inline int imx_dma_sg_next(int channel, struct scatterlist *sg)
+{
+        struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+        unsigned long now;
+
+        if (!imxdma->name) {
+                printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
+                       __func__, channel);
+                return 0;
+        }
+
+        now = min(imxdma->resbytes, sg->length);
+        imxdma->resbytes -= now;
+
+        if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
+                __raw_writel(sg->dma_address, DMA_BASE + DMA_DAR(channel));
+        else
+                __raw_writel(sg->dma_address, DMA_BASE + DMA_SAR(channel));
+
+        __raw_writel(now, DMA_BASE + DMA_CNTR(channel));
+
+        pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
+                "size 0x%08x\n", channel,
+                 __raw_readl(DMA_BASE + DMA_DAR(channel)),
+                 __raw_readl(DMA_BASE + DMA_SAR(channel)),
+                 __raw_readl(DMA_BASE + DMA_CNTR(channel)));
+
+        return now;
+}
+
+/**
+ * imx_dma_setup_single - setup i.MX DMA channel for linear memory to/from
+ * device transfer
+ *
+ * @channel: i.MX DMA channel number
+ * @dma_address: the DMA/physical memory address of the linear data block
+ *              to transfer
+ * @dma_length: length of the data block in bytes
+ * @dev_addr: physical device port address
+ * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
+ *           or %DMA_MODE_WRITE from memory to the device
+ *
+ * Return value: if incorrect parameters are provided -%EINVAL.
+ *              Zero indicates success.
+ */
+int
+imx_dma_setup_single(int channel, dma_addr_t dma_address,
+                     unsigned int dma_length, unsigned int dev_addr,
+                     dmamode_t dmamode)
+{
+        struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+
+        imxdma->sg = NULL;
+        imxdma->dma_mode = dmamode;
+
+        if (!dma_address) {
+                printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
+                       channel);
+                return -EINVAL;
+        }
+
+        if (!dma_length) {
+                printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
+                       channel);
+                return -EINVAL;
+        }
+
+        if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
+                pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
+                        "dev_addr=0x%08x for read\n",
+                        channel, __func__, (unsigned int)dma_address,
+                        dma_length, dev_addr);
+
+                __raw_writel(dev_addr, DMA_BASE + DMA_SAR(channel));
+                __raw_writel(dma_address, DMA_BASE + DMA_DAR(channel));
+                __raw_writel(imxdma->ccr_from_device,
+                                DMA_BASE + DMA_CCR(channel));
+        } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
+                pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
+                        "dev_addr=0x%08x for write\n",
+                        channel, __func__, (unsigned int)dma_address,
+                        dma_length, dev_addr);
+
+                __raw_writel(dma_address, DMA_BASE + DMA_SAR(channel));
+                __raw_writel(dev_addr, DMA_BASE + DMA_DAR(channel));
+                __raw_writel(imxdma->ccr_to_device,
+                                DMA_BASE + DMA_CCR(channel));
+        } else {
+                printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
+                       channel);
+                return -EINVAL;
+        }
+
+        __raw_writel(dma_length, DMA_BASE + DMA_CNTR(channel));
+
+        return 0;
+}
+EXPORT_SYMBOL(imx_dma_setup_single);
+
+/**
+ * imx_dma_setup_sg - setup i.MX DMA channel SG list to/from device transfer
+ * @channel: i.MX DMA channel number
+ * @sg: pointer to the scatter-gather list/vector
+ * @sgcount: scatter-gather list hungs count
+ * @dma_length: total length of the transfer request in bytes
+ * @dev_addr: physical device port address
+ * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
+ *           or %DMA_MODE_WRITE from memory to the device
+ *
+ * The function sets up DMA channel state and registers to be ready for
+ * transfer specified by provided parameters. The scatter-gather emulation
+ * is set up according to the parameters.
+ *
+ * The full preparation of the transfer requires setup of more register
+ * by the caller before imx_dma_enable() can be called.
+ *
+ * %BLR(channel) holds transfer burst length in bytes, 0 means 64 bytes
+ *
+ * %RSSR(channel) has to be set to the DMA request line source %DMA_REQ_xxx
+ *
+ * %CCR(channel) has to specify transfer parameters, the next settings is
+ * typical for linear or simple scatter-gather transfers if %DMA_MODE_READ is
+ * specified
+ *
+ * %CCR_DMOD_LINEAR | %CCR_DSIZ_32 | %CCR_SMOD_FIFO | %CCR_SSIZ_x
+ *
+ * The typical setup for %DMA_MODE_WRITE is specified by next options
+ * combination
+ *
+ * %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x
+ *
+ * Be careful here and do not mistakenly mix source and target device
+ * port sizes constants, they are really different:
+ * %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32,
+ * %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32
+ *
+ * Return value: if incorrect parameters are provided -%EINVAL.
+ * Zero indicates success.
+ */
+int
+imx_dma_setup_sg(int channel,
+                 struct scatterlist *sg, unsigned int sgcount,
+                 unsigned int dma_length, unsigned int dev_addr,
+                 dmamode_t dmamode)
+{
+        struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+
+        if (imxdma->in_use)
+                return -EBUSY;
+
+        imxdma->sg = sg;
+        imxdma->dma_mode = dmamode;
+        imxdma->resbytes = dma_length;
+
+        if (!sg || !sgcount) {
+                printk(KERN_ERR "imxdma%d: imx_dma_setup_sg epty sg list\n",
+                       channel);
+                return -EINVAL;
+        }
+
+        if (!sg->length) {
+                printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
+                       channel);
+                return -EINVAL;
+        }
+
+        if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
+                pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
+                        "dev_addr=0x%08x for read\n",
+                        channel, __func__, sg, sgcount, dma_length, dev_addr);
+
+                __raw_writel(dev_addr, DMA_BASE + DMA_SAR(channel));
+                __raw_writel(imxdma->ccr_from_device,
+                                DMA_BASE + DMA_CCR(channel));
+        } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
+                pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
+                        "dev_addr=0x%08x for write\n",
+                        channel, __func__, sg, sgcount, dma_length, dev_addr);
+
+                __raw_writel(dev_addr, DMA_BASE + DMA_DAR(channel));
+                __raw_writel(imxdma->ccr_to_device,
+                                DMA_BASE + DMA_CCR(channel));
+        } else {
+                printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
+                       channel);
+                return -EINVAL;
+        }
+
+        imx_dma_sg_next(channel, sg);
+
+        return 0;
+}
+EXPORT_SYMBOL(imx_dma_setup_sg);
+
+int
+imx_dma_config_channel(int channel, unsigned int config_port,
+        unsigned int config_mem, unsigned int dmareq, int hw_chaining)
+{
+        struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+        u32 dreq = 0;
+
+        imxdma->hw_chaining = 0;
+
+        if (hw_chaining) {
+                imxdma->hw_chaining = 1;
+                if (!imx_dma_hw_chain(imxdma))
+                        return -EINVAL;
+        }
+
+        if (dmareq)
+                dreq = CCR_REN;
+
+        imxdma->ccr_from_device = config_port | (config_mem << 2) | dreq;
+        imxdma->ccr_to_device = config_mem | (config_port << 2) | dreq;
+
+        __raw_writel(dmareq, DMA_BASE + DMA_RSSR(channel));
+
+        return 0;
+}
+EXPORT_SYMBOL(imx_dma_config_channel);
+
+void imx_dma_config_burstlen(int channel, unsigned int burstlen)
+{
+        __raw_writel(burstlen, DMA_BASE + DMA_BLR(channel));
+}
+EXPORT_SYMBOL(imx_dma_config_burstlen);
+
+/**
+ * imx_dma_setup_handlers - setup i.MX DMA channel end and error notification
+ * handlers
+ * @channel: i.MX DMA channel number
+ * @irq_handler: the pointer to the function called if the transfer
+ *              ends successfully
+ * @err_handler: the pointer to the function called if the premature
+ *              end caused by error occurs
+ * @data: user specified value to be passed to the handlers
+ */
+int
+imx_dma_setup_handlers(int channel,
+                       void (*irq_handler) (int, void *),
+                       void (*err_handler) (int, void *, int),
+                       void *data)
+{
+        struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+        unsigned long flags;
+
+        if (!imxdma->name) {
+                printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
+                       __func__, channel);
+                return -ENODEV;
+        }
+
+        local_irq_save(flags);
+        __raw_writel(1 << channel, DMA_BASE + DMA_DISR);
+        imxdma->irq_handler = irq_handler;
+        imxdma->err_handler = err_handler;
+        imxdma->data = data;
+        local_irq_restore(flags);
+        return 0;
+}
+EXPORT_SYMBOL(imx_dma_setup_handlers);
+
+/**
+ * imx_dma_setup_progression_handler - setup i.MX DMA channel progression
+ * handlers
+ * @channel: i.MX DMA channel number
+ * @prog_handler: the pointer to the function called if the transfer progresses
+ */
+int
+imx_dma_setup_progression_handler(int channel,
+                        void (*prog_handler) (int, void*, struct scatterlist*))
+{
+        struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+        unsigned long flags;
+
+        if (!imxdma->name) {
+                printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
+                       __func__, channel);
+                return -ENODEV;
+        }
+
+        local_irq_save(flags);
+        imxdma->prog_handler = prog_handler;
+        local_irq_restore(flags);
+        return 0;
+}
+EXPORT_SYMBOL(imx_dma_setup_progression_handler);
+
+/**
+ * imx_dma_enable - function to start i.MX DMA channel operation
+ * @channel: i.MX DMA channel number
+ *
+ * The channel has to be allocated by driver through imx_dma_request()
+ * or imx_dma_request_by_prio() function.
+ * The transfer parameters has to be set to the channel registers through
+ * call of the imx_dma_setup_single() or imx_dma_setup_sg() function
+ * and registers %BLR(channel), %RSSR(channel) and %CCR(channel) has to
+ * be set prior this function call by the channel user.
+ */
+void imx_dma_enable(int channel)
+{
+        struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+        unsigned long flags;
+
+        pr_debug("imxdma%d: imx_dma_enable\n", channel);
+
+        if (!imxdma->name) {
+                printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
+                       __func__, channel);
+                return;
+        }
+
+        if (imxdma->in_use)
+                return;
+
+        local_irq_save(flags);
+
+        __raw_writel(1 << channel, DMA_BASE + DMA_DISR);
+        __raw_writel(__raw_readl(DMA_BASE + DMA_DIMR) & ~(1 << channel),
+                DMA_BASE + DMA_DIMR);
+        __raw_writel(__raw_readl(DMA_BASE + DMA_CCR(channel)) | CCR_CEN |
+                CCR_ACRPT,
+                DMA_BASE + DMA_CCR(channel));
+
+#ifdef CONFIG_ARCH_MX2
+        if (imxdma->sg && imx_dma_hw_chain(imxdma)) {
+                imxdma->sg = sg_next(imxdma->sg);
+                if (imxdma->sg) {
+                        u32 tmp;
+                        imx_dma_sg_next(channel, imxdma->sg);
+                        tmp = __raw_readl(DMA_BASE + DMA_CCR(channel));
+                        __raw_writel(tmp | CCR_RPT | CCR_ACRPT,
+                                DMA_BASE + DMA_CCR(channel));
+                }
+        }
+#endif
+        imxdma->in_use = 1;
+
+        local_irq_restore(flags);
+}
+EXPORT_SYMBOL(imx_dma_enable);
+
+/**
+ * imx_dma_disable - stop, finish i.MX DMA channel operatin
+ * @channel: i.MX DMA channel number
+ */
+void imx_dma_disable(int channel)
+{
+        struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+        unsigned long flags;
+
+        pr_debug("imxdma%d: imx_dma_disable\n", channel);
+
+        if (imx_dma_hw_chain(imxdma))
+                del_timer(&imxdma->watchdog);
+
+        local_irq_save(flags);
+        __raw_writel(__raw_readl(DMA_BASE + DMA_DIMR) | (1 << channel),
+                DMA_BASE + DMA_DIMR);
+        __raw_writel(__raw_readl(DMA_BASE + DMA_CCR(channel)) & ~CCR_CEN,
+                DMA_BASE + DMA_CCR(channel));
+        __raw_writel(1 << channel, DMA_BASE + DMA_DISR);
+        imxdma->in_use = 0;
+        local_irq_restore(flags);
+}
+EXPORT_SYMBOL(imx_dma_disable);
+
+static void imx_dma_watchdog(unsigned long chno)
+{
+        struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
+
+        __raw_writel(0, DMA_BASE + DMA_CCR(chno));
+        imxdma->in_use = 0;
+        imxdma->sg = NULL;
+
+        if (imxdma->err_handler)
+                imxdma->err_handler(chno, imxdma->data, IMX_DMA_ERR_TIMEOUT);
+}
+
+static irqreturn_t dma_err_handler(int irq, void *dev_id)
+{
+        int i, disr;
+        struct imx_dma_channel *imxdma;
+        unsigned int err_mask;
+        int errcode;
+
+        disr = __raw_readl(DMA_BASE + DMA_DISR);
+
+        err_mask = __raw_readl(DMA_BASE + DMA_DBTOSR) |
+                   __raw_readl(DMA_BASE + DMA_DRTOSR) |
+                   __raw_readl(DMA_BASE + DMA_DSESR)  |
+                   __raw_readl(DMA_BASE + DMA_DBOSR);
+
+        if (!err_mask)
+                return IRQ_HANDLED;
+
+        __raw_writel(disr & err_mask, DMA_BASE + DMA_DISR);
+
+        for (i = 0; i < IMX_DMA_CHANNELS; i++) {
+                if (!(err_mask & (1 << i)))
+                        continue;
+                imxdma = &imx_dma_channels[i];
+                errcode = 0;
+
+                if (__raw_readl(DMA_BASE + DMA_DBTOSR) & (1 << i)) {
+                        __raw_writel(1 << i, DMA_BASE + DMA_DBTOSR);
+                        errcode |= IMX_DMA_ERR_BURST;
+                }
+                if (__raw_readl(DMA_BASE + DMA_DRTOSR) & (1 << i)) {
+                        __raw_writel(1 << i, DMA_BASE + DMA_DRTOSR);
+                        errcode |= IMX_DMA_ERR_REQUEST;
+                }
+                if (__raw_readl(DMA_BASE + DMA_DSESR) & (1 << i)) {
+                        __raw_writel(1 << i, DMA_BASE + DMA_DSESR);
+                        errcode |= IMX_DMA_ERR_TRANSFER;
+                }
+                if (__raw_readl(DMA_BASE + DMA_DBOSR) & (1 << i)) {
+                        __raw_writel(1 << i, DMA_BASE + DMA_DBOSR);
+                        errcode |= IMX_DMA_ERR_BUFFER;
+                }
+                if (imxdma->name && imxdma->err_handler) {
+                        imxdma->err_handler(i, imxdma->data, errcode);
+                        continue;
+                }
+
+                imx_dma_channels[i].sg = NULL;
+
+                printk(KERN_WARNING
+                       "DMA timeout on channel %d (%s) -%s%s%s%s\n",
+                       i, imxdma->name,
+                       errcode & IMX_DMA_ERR_BURST ?    " burst" : "",
+                       errcode & IMX_DMA_ERR_REQUEST ?  " request" : "",
+                       errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
+                       errcode & IMX_DMA_ERR_BUFFER ?   " buffer" : "");
+        }
+        return IRQ_HANDLED;
+}
+
+static void dma_irq_handle_channel(int chno)
+{
+        struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
+
+        if (!imxdma->name) {
+                /*
+                 * IRQ for an unregistered DMA channel:
+                 * let's clear the interrupts and disable it.
+                 */
+                printk(KERN_WARNING
+                       "spurious IRQ for DMA channel %d\n", chno);
+                return;
+        }
+
+        if (imxdma->sg) {
+                u32 tmp;
+                struct scatterlist *current_sg = imxdma->sg;
+                imxdma->sg = sg_next(imxdma->sg);
+
+                if (imxdma->sg) {
+                        imx_dma_sg_next(chno, imxdma->sg);
+
+                        tmp = __raw_readl(DMA_BASE + DMA_CCR(chno));
+
+                        if (imx_dma_hw_chain(imxdma)) {
+                                /* FIXME: The timeout should probably be
+                                 * configurable
+                                 */
+                                mod_timer(&imxdma->watchdog,
+                                        jiffies + msecs_to_jiffies(500));
+
+                                tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
+                                __raw_writel(tmp, DMA_BASE +
+                                                DMA_CCR(chno));
+                        } else {
+                                __raw_writel(tmp & ~CCR_CEN, DMA_BASE +
+                                                DMA_CCR(chno));
+                                tmp |= CCR_CEN;
+                        }
+
+                        __raw_writel(tmp, DMA_BASE + DMA_CCR(chno));
+
+                        if (imxdma->prog_handler)
+                                imxdma->prog_handler(chno, imxdma->data,
+                                                current_sg);
+
+                        return;
+                }
+
+                if (imx_dma_hw_chain(imxdma)) {
+                        del_timer(&imxdma->watchdog);
+                        return;
+                }
+        }
+
+        __raw_writel(0, DMA_BASE + DMA_CCR(chno));
+        imxdma->in_use = 0;
+        if (imxdma->irq_handler)
+                imxdma->irq_handler(chno, imxdma->data);
+}
+
+static irqreturn_t dma_irq_handler(int irq, void *dev_id)
+{
+        int i, disr;
+
+#ifdef CONFIG_ARCH_MX2
+        dma_err_handler(irq, dev_id);
+#endif
+
+        disr = __raw_readl(DMA_BASE + DMA_DISR);
+
+        pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
+                     disr);
+
+        __raw_writel(disr, DMA_BASE + DMA_DISR);
+        for (i = 0; i < IMX_DMA_CHANNELS; i++) {
+                if (disr & (1 << i))
+                        dma_irq_handle_channel(i);
+        }
+
+        return IRQ_HANDLED;
+}
+
+/**
+ * imx_dma_request - request/allocate specified channel number
+ * @channel: i.MX DMA channel number
+ * @name: the driver/caller own non-%NULL identification
+ */
+int imx_dma_request(int channel, const char *name)
+{
+        struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+        unsigned long flags;
+        int ret;
+
+        /* basic sanity checks */
+        if (!name)
+                return -EINVAL;
+
+        if (channel >= IMX_DMA_CHANNELS) {
+                printk(KERN_CRIT "%s: called for  non-existed channel %d\n",
+                       __func__, channel);
+                return -EINVAL;
+        }
+
+        local_irq_save(flags);
+        if (imxdma->name) {
+                local_irq_restore(flags);
+                return -EBUSY;
+        }
+
+#ifdef CONFIG_ARCH_MX2
+        ret = request_irq(MXC_INT_DMACH0 + channel, dma_irq_handler, 0, "DMA",
+                        NULL);
+        if (ret) {
+                printk(KERN_CRIT "Can't register IRQ %d for DMA channel %d\n",
+                                MXC_INT_DMACH0 + channel, channel);
+                return ret;
+        }
+        init_timer(&imxdma->watchdog);
+        imxdma->watchdog.function = &imx_dma_watchdog;
+        imxdma->watchdog.data = channel;
+#endif
+
+        imxdma->name = name;
+        imxdma->irq_handler = NULL;
+        imxdma->err_handler = NULL;
+        imxdma->data = NULL;
+        imxdma->sg = NULL;
+
+        local_irq_restore(flags);
+        return 0;
+}
+EXPORT_SYMBOL(imx_dma_request);
+
+/**
+ * imx_dma_free - release previously acquired channel
+ * @channel: i.MX DMA channel number
+ */
+void imx_dma_free(int channel)
+{
+        unsigned long flags;
+        struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+
+        if (!imxdma->name) {
+                printk(KERN_CRIT
+                       "%s: trying to free free channel %d\n",
+                       __func__, channel);
+                return;
+        }
+
+        local_irq_save(flags);
+        /* Disable interrupts */
+        __raw_writel(__raw_readl(DMA_BASE + DMA_DIMR) | (1 << channel),
+                DMA_BASE + DMA_DIMR);
+        __raw_writel(__raw_readl(DMA_BASE + DMA_CCR(channel)) & ~CCR_CEN,
+                DMA_BASE + DMA_CCR(channel));
+        imxdma->name = NULL;
+
+#ifdef CONFIG_ARCH_MX2
+        free_irq(MXC_INT_DMACH0 + channel, NULL);
+#endif
+
+        local_irq_restore(flags);
+}
+EXPORT_SYMBOL(imx_dma_free);
+
+/**
+ * imx_dma_request_by_prio - find and request some of free channels best
+ * suiting requested priority
+ * @channel: i.MX DMA channel number
+ * @name: the driver/caller own non-%NULL identification
+ *
+ * This function tries to find a free channel in the specified priority group
+ * This function tries to find a free channel in the specified priority group
+ * if the priority cannot be achieved it tries to look for free channel
+ * in the higher and then even lower priority groups.
+ *
+ * Return value: If there is no free channel to allocate, -%ENODEV is returned.
+ *               On successful allocation channel is returned.
+ */
+int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio)
+{
+        int i;
+        int best;
+
+        switch (prio) {
+        case (DMA_PRIO_HIGH):
+                best = 8;
+                break;
+        case (DMA_PRIO_MEDIUM):
+                best = 4;
+                break;
+        case (DMA_PRIO_LOW):
+        default:
+                best = 0;
+                break;
+        }
+
+        for (i = best; i < IMX_DMA_CHANNELS; i++)
+                if (!imx_dma_request(i, name))
+                        return i;
+
+        for (i = best - 1; i >= 0; i--)
+                if (!imx_dma_request(i, name))
+                        return i;
+
+        printk(KERN_ERR "%s: no free DMA channel found\n", __func__);
+
+        return -ENODEV;
+}
+EXPORT_SYMBOL(imx_dma_request_by_prio);
+
+static int __init imx_dma_init(void)
+{
+        int ret = 0;
+        int i;
+
+        dma_clk = clk_get(NULL, "dma_clk");
+        clk_enable(dma_clk);
+
+        /* reset DMA module */
+        __raw_writel(DCR_DRST, DMA_BASE + DMA_DCR);
+
+#ifdef CONFIG_ARCH_MX1
+        ret = request_irq(DMA_INT, dma_irq_handler, 0, "DMA", NULL);
+        if (ret) {
+                printk(KERN_CRIT "Wow!  Can't register IRQ for DMA\n");
+                return ret;
+        }
+
+        ret = request_irq(DMA_ERR, dma_err_handler, 0, "DMA", NULL);
+        if (ret) {
+                printk(KERN_CRIT "Wow!  Can't register ERRIRQ for DMA\n");
+                free_irq(DMA_INT, NULL);
+                return ret;
+        }
+#endif
+        /* enable DMA module */
+        __raw_writel(DCR_DEN, DMA_BASE + DMA_DCR);
+
+        /* clear all interrupts */
+        __raw_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_BASE + DMA_DISR);
+
+        /* disable interrupts */
+        __raw_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_BASE + DMA_DIMR);
+
+        for (i = 0; i < IMX_DMA_CHANNELS; i++) {
+                imx_dma_channels[i].sg = NULL;
+                imx_dma_channels[i].dma_num = i;
+        }
+
+        return ret;
+}
+
+arch_initcall(imx_dma_init);
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
index 1bc6fb0f9a83..745b48864f93 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31ads.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
@@ -90,6 +90,9 @@
 #define PBC_INTMASK_CLEAR_REG   (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
 #define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
 
+#define MXC_EXP_IO_BASE         (MXC_MAX_INT_LINES + MXC_MAX_GPIO_LINES)
+#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_EXP_IO_BASE)
+
 #define EXPIO_INT_LOW_BAT       (MXC_EXP_IO_BASE + 0)
 #define EXPIO_INT_PB_IRQ        (MXC_EXP_IO_BASE + 1)
 #define EXPIO_INT_OTG_FS_OVR    (MXC_EXP_IO_BASE + 2)
diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h
index 24caa2b7c91d..d21f78e78819 100644
--- a/arch/arm/plat-mxc/include/mach/clock.h
+++ b/arch/arm/plat-mxc/include/mach/clock.h
@@ -39,7 +39,7 @@ struct clk {
         /* Register bit position for clock's enable/disable control. */
         u8 enable_shift;
         /* Register address for clock's enable/disable control. */
-        u32 enable_reg;
+        void __iomem *enable_reg;
         u32 flags;
         /* get the current clock rate (always a fresh value) */
         unsigned long (*get_rate) (struct clk *);
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index a6d2e24aab15..6350287a59b9 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -11,10 +11,13 @@
 #ifndef __ASM_ARCH_MXC_COMMON_H__
 #define __ASM_ARCH_MXC_COMMON_H__
 
+struct platform_device;
+
 extern void mxc_map_io(void);
 extern void mxc_init_irq(void);
 extern void mxc_timer_init(const char *clk_timer);
 extern int mxc_clocks_init(unsigned long fref);
 extern int mxc_register_gpios(void);
+extern int mxc_register_device(struct platform_device *pdev, void *data);
 
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
new file mode 100644
index 000000000000..e85fd946116c
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
@@ -0,0 +1,89 @@
+/*
+ *  linux/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
+ *
+ *  i.MX DMA registration and IRQ dispatching
+ *
+ * Copyright 2006 Pavel Pisa <pisa@cmp.felk.cvut.cz>
+ * Copyright 2008 Juergen Beisert, <kernel@pengutronix.de>
+ * Copyright 2008 Sascha Hauer, <s.hauer@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <asm/dma.h>
+
+#ifndef __ASM_ARCH_MXC_DMA_H
+#define __ASM_ARCH_MXC_DMA_H
+
+#define IMX_DMA_CHANNELS  16
+
+#define DMA_BASE IO_ADDRESS(DMA_BASE_ADDR)
+
+#define IMX_DMA_MEMSIZE_32      (0 << 4)
+#define IMX_DMA_MEMSIZE_8       (1 << 4)
+#define IMX_DMA_MEMSIZE_16      (2 << 4)
+#define IMX_DMA_TYPE_LINEAR     (0 << 10)
+#define IMX_DMA_TYPE_2D         (1 << 10)
+#define IMX_DMA_TYPE_FIFO       (2 << 10)
+
+#define IMX_DMA_ERR_BURST     (1 << 0)
+#define IMX_DMA_ERR_REQUEST   (1 << 1)
+#define IMX_DMA_ERR_TRANSFER  (1 << 2)
+#define IMX_DMA_ERR_BUFFER    (1 << 3)
+#define IMX_DMA_ERR_TIMEOUT   (1 << 4)
+
+int
+imx_dma_config_channel(int channel, unsigned int config_port,
+        unsigned int config_mem, unsigned int dmareq, int hw_chaining);
+
+void
+imx_dma_config_burstlen(int channel, unsigned int burstlen);
+
+int
+imx_dma_setup_single(int channel, dma_addr_t dma_address,
+                unsigned int dma_length, unsigned int dev_addr,
+                dmamode_t dmamode);
+
+int
+imx_dma_setup_sg(int channel, struct scatterlist *sg,
+                unsigned int sgcount, unsigned int dma_length,
+                unsigned int dev_addr, dmamode_t dmamode);
+
+int
+imx_dma_setup_handlers(int channel,
+                void (*irq_handler) (int, void *),
+                void (*err_handler) (int, void *, int), void *data);
+
+int
+imx_dma_setup_progression_handler(int channel,
+                void (*prog_handler) (int, void*, struct scatterlist*));
+
+void imx_dma_enable(int channel);
+
+void imx_dma_disable(int channel);
+
+int imx_dma_request(int channel, const char *name);
+
+void imx_dma_free(int channel);
+
+enum imx_dma_prio {
+        DMA_PRIO_HIGH = 0,
+        DMA_PRIO_MEDIUM = 1,
+        DMA_PRIO_LOW = 2
+};
+
+int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio);
+
+#endif  /* _ASM_ARCH_MXC_DMA_H */
diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S
index b542433afb1b..11632028f7d1 100644
--- a/arch/arm/plat-mxc/include/mach/entry-macro.S
+++ b/arch/arm/plat-mxc/include/mach/entry-macro.S
@@ -9,11 +9,17 @@
  * published by the Free Software Foundation.
  */
 
+#define AVIC_NIMASK     0x04
+
         @ this macro disables fast irq (not implemented)
         .macro  disable_fiq
         .endm
 
         .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =AVIC_IO_ADDRESS(AVIC_BASE_ADDR)
+#ifdef CONFIG_MXC_IRQ_PRIOR
+        ldr     r4, [\base, #AVIC_NIMASK]
+#endif
         .endm
 
         .macro  arch_ret_to_user, tmp1, tmp2
@@ -23,7 +29,6 @@
         @ and returns its number in irqnr
         @ and returns if an interrupt occured in irqstat
         .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        ldr     \base, =AVIC_IO_ADDRESS(AVIC_BASE_ADDR)
         @ Load offset & priority of the highest priority
         @ interrupt pending from AVIC_NIVECSR
         ldr     \irqstat, [\base, #0x40]
@@ -32,6 +37,11 @@
         mov     \irqnr, \irqstat, asr #16
         @ set zero flag if IRQ + 1 == 0
         adds    \tmp, \irqnr, #1
+#ifdef CONFIG_MXC_IRQ_PRIOR
+        bicne   \tmp, \irqstat, #0xFFFFFFE0
+        strne   \tmp, [\base, #AVIC_NIMASK]
+        streq   r4, [\base, #AVIC_NIMASK]
+#endif
         .endm
 
         @ irq priority table (not used)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h
index 076d37b38eb2..3d09bfd6c53d 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h
@@ -247,6 +247,11 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
 #endif
 
 #ifdef CONFIG_ARCH_MX2
+#define PA0_PF_USBH2_CLK        (GPIO_PORTA | GPIO_PF | 0)
+#define PA1_PF_USBH2_DIR        (GPIO_PORTA | GPIO_PF | 1)
+#define PA2_PF_USBH2_DATA7      (GPIO_PORTA | GPIO_PF | 2)
+#define PA3_PF_USBH2_NXT        (GPIO_PORTA | GPIO_PF | 3)
+#define PA4_PF_USBH2_STP        (GPIO_PORTA | GPIO_PF | 4)
 #define PA5_PF_LSCLK            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 5)
 #define PA6_PF_LD0              (GPIO_PORTA | GPIO_OUT | GPIO_PF | 6)
 #define PA7_PF_LD1              (GPIO_PORTA | GPIO_OUT | GPIO_PF | 7)
@@ -294,6 +299,16 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
 #define PB20_AF_UART5_CTS       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 20)
 #define PB21_PF_CSI_HSYNC       (GPIO_PORTB | GPIO_OUT | GPIO_PF | 21)
 #define PB21_AF_UART5_RTS       (GPIO_PORTB | GPIO_IN  | GPIO_AF | 21)
+#define PB22_PF_USBH1_SUSP      (GPIO_PORTB | GPIO_PF | 22)
+#define PB23_PF_USB_PWR         (GPIO_PORTB | GPIO_PF | 23)
+#define PB24_PF_USB_OC_B        (GPIO_PORTB | GPIO_PF | 24)
+#define PB25_PF_USBH1_RCV       (GPIO_PORTB | GPIO_PF | 25)
+#define PB26_PF_USBH1_FS        (GPIO_PORTB | GPIO_PF | 26)
+#define PB27_PF_USBH1_OE_B      (GPIO_PORTB | GPIO_PF | 27)
+#define PB28_PF_USBH1_TXDM      (GPIO_PORTB | GPIO_PF | 28)
+#define PB29_PF_USBH1_TXDP      (GPIO_PORTB | GPIO_PF | 29)
+#define PB30_PF_USBH1_RXDM      (GPIO_PORTB | GPIO_PF | 30)
+#define PB31_PF_USBH1_RXDP      (GPIO_PORTB | GPIO_PF | 31)
 #define PB26_AF_UART4_RTS       (GPIO_PORTB | GPIO_IN  | GPIO_PF | 26)
 #define PB28_AF_UART4_TXD       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 28)
 #define PB29_AF_UART4_CTS       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 29)
@@ -335,8 +350,15 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
 #define PD16_AIN_FEC_TX_ER      (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16)
 #define PD17_PF_I2C_DATA        (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
 #define PD18_PF_I2C_CLK         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
+#define PD19_AF_USBH2_DATA4     (GPIO_PORTD | GPIO_AF | 19)
+#define PD20_AF_USBH2_DATA3     (GPIO_PORTD | GPIO_AF | 20)
+#define PD21_AF_USBH2_DATA6     (GPIO_PORTD | GPIO_AF | 21)
+#define PD22_AF_USBH2_DATA0     (GPIO_PORTD | GPIO_AF | 22)
+#define PD23_AF_USBH2_DATA2     (GPIO_PORTD | GPIO_AF | 23)
+#define PD24_AF_USBH2_DATA1     (GPIO_PORTD | GPIO_AF | 24)
 #define PD25_PF_CSPI1_RDY       (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 25)
 #define PD26_PF_CSPI1_SS2       (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 26)
+#define PD26_AF_USBH2_DATA5     (GPIO_PORTD | GPIO_AF | 26)
 #define PD27_PF_CSPI1_SS1       (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 27)
 #define PD28_PF_CSPI1_SS0       (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 28)
 #define PD29_PF_CSPI1_SCLK      (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 29)
@@ -355,6 +377,8 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
 #define PE13_PF_UART1_RXD       (GPIO_PORTE | GPIO_IN  | GPIO_PF | 13)
 #define PE14_PF_UART1_CTS       (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14)
 #define PE15_PF_UART1_RTS       (GPIO_PORTE | GPIO_IN  | GPIO_PF | 15)
+#define PE16_AF_RTCK            (GPIO_PORTE | GPIO_OUT | GPIO_AF | 16)
+#define PE16_PF_RTCK            (GPIO_PORTE | GPIO_OUT | GPIO_PF | 16)
 #define PE18_AF_CSPI3_MISO      (GPIO_PORTE | GPIO_IN  | GPIO_AF | 18)
 #define PE21_AF_CSPI3_SS        (GPIO_PORTE | GPIO_OUT | GPIO_AF | 21)
 #define PE22_AF_CSPI3_MOSI      (GPIO_PORTE | GPIO_OUT | GPIO_AF | 22)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index 7509e7692f08..c9f39c2fb8c6 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -491,6 +491,26 @@ enum iomux_pins {
 #define MX31_PIN_RTS1__RTS1             IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_TXD1__TXD1             IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_RXD1__RXD1             IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI1_MOSI__MOSI       IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI1_MISO__MISO       IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI1_SCLK__SCLK       IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI1_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI1_SS0__SS0         IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI1_SS1__SS1         IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI1_SS2__SS2         IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI2_MOSI__MOSI       IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI2_MISO__MISO       IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI2_SCLK__SCLK       IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI2_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI2_SPI_RDY, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI2_SS0__SS0         IOMUX_MODE(MX31_PIN_CSPI2_SS0, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI2_SS1__SS1         IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI2_SS2__SS2         IOMUX_MODE(MX31_PIN_CSPI2_SS2, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI3_MOSI__MOSI       IOMUX_MODE(MX31_PIN_CSPI3_MOSI, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI3_MISO__MISO       IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI3_SCLK__SCLK       IOMUX_MODE(MX31_PIN_CSPI3_SCLK, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI3_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_FUNC)
+/*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0
+ * cspi1_ss1*/
 
 /*
  * This function configures the pad value for a IOMUX pin.
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index 228c4f68ccdf..b55bba35e18a 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -12,5 +12,6 @@
 #define __ASM_ARCH_MXC_IRQS_H__
 
 #include <mach/hardware.h>
+extern void imx_irq_set_priority(unsigned char irq, unsigned char prio);
 
 #endif /* __ASM_ARCH_MXC_IRQS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index 212ecc246626..a86db64744a1 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -128,6 +128,7 @@
  * it returns 0xDEADBEEF
  */
 #define IO_ADDRESS(x)   \
+        (void __iomem *) \
         (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \
                 AIPI_IO_ADDRESS(x) : \
         ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index a7373e4a56cb..0536f8917bc0 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -198,6 +198,7 @@
  * it returns 0xDEADBEEF
  */
 #define IO_ADDRESS(x)   \
+        (void __iomem *) \
         (((x >= IRAM_BASE_ADDR) && (x < (IRAM_BASE_ADDR + IRAM_SIZE))) ? IRAM_IO_ADDRESS(x):\
         ((x >= L2CC_BASE_ADDR) && (x < (L2CC_BASE_ADDR + L2CC_SIZE))) ? L2CC_IO_ADDRESS(x):\
         ((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 332eda4dbd3b..f6caab062131 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -33,4 +33,10 @@
 # define cpu_is_mx27() (0)
 #endif
 
+#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2)
+#define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10)
+#define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x4)
+#define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x8)
+#endif
+
 #endif /*  __ASM_ARCH_MXC_H__ */
diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c
index c6b837893d87..d862c9e5f8db 100644
--- a/arch/arm/plat-mxc/irq.c
+++ b/arch/arm/plat-mxc/irq.c
@@ -30,14 +30,7 @@
 #define AVIC_INTENABLEL         (AVIC_BASE + 0x14)      /* int enable reg low */
 #define AVIC_INTTYPEH           (AVIC_BASE + 0x18)      /* int type reg high */
 #define AVIC_INTTYPEL           (AVIC_BASE + 0x1C)      /* int type reg low */
-#define AVIC_NIPRIORITY7        (AVIC_BASE + 0x20)      /* norm int priority lvl7 */
-#define AVIC_NIPRIORITY6        (AVIC_BASE + 0x24)      /* norm int priority lvl6 */
-#define AVIC_NIPRIORITY5        (AVIC_BASE + 0x28)      /* norm int priority lvl5 */
-#define AVIC_NIPRIORITY4        (AVIC_BASE + 0x2C)      /* norm int priority lvl4 */
-#define AVIC_NIPRIORITY3        (AVIC_BASE + 0x30)      /* norm int priority lvl3 */
-#define AVIC_NIPRIORITY2        (AVIC_BASE + 0x34)      /* norm int priority lvl2 */
-#define AVIC_NIPRIORITY1        (AVIC_BASE + 0x38)      /* norm int priority lvl1 */
-#define AVIC_NIPRIORITY0        (AVIC_BASE + 0x3C)      /* norm int priority lvl0 */
+#define AVIC_NIPRIORITY(x)      (AVIC_BASE + (0x20 + 4 * (7 - (x)))) /* int priority */
 #define AVIC_NIVECSR            (AVIC_BASE + 0x40)      /* norm int vector/status */
 #define AVIC_FIVECSR            (AVIC_BASE + 0x44)      /* fast int vector/status */
 #define AVIC_INTSRCH            (AVIC_BASE + 0x48)      /* int source reg high */
@@ -54,6 +47,24 @@
 #define IIM_PROD_REV_SH         3
 #define IIM_PROD_REV_LEN        5
 
+#ifdef CONFIG_MXC_IRQ_PRIOR
+void imx_irq_set_priority(unsigned char irq, unsigned char prio)
+{
+        unsigned int temp;
+        unsigned int mask = 0x0F << irq % 8 * 4;
+
+        if (irq > 63)
+                return;
+
+        temp = __raw_readl(AVIC_NIPRIORITY(irq / 8));
+        temp &= ~mask;
+        temp |= prio & mask;
+
+        __raw_writel(temp, AVIC_NIPRIORITY(irq / 8));
+}
+EXPORT_SYMBOL(imx_irq_set_priority);
+#endif
+
 /* Disable interrupt number "irq" in the AVIC */
 static void mxc_mask_irq(unsigned int irq)
 {
@@ -101,10 +112,9 @@ void __init mxc_init_irq(void)
                 set_irq_flags(i, IRQF_VALID);
         }
 
-        /* Set WDOG2's interrupt the highest priority level (bit 28-31) */
-        reg = __raw_readl(AVIC_NIPRIORITY6);
-        reg |= (0xF << 28);
-        __raw_writel(reg, AVIC_NIPRIORITY6);
+        /* Set default priority value (0) for all IRQ's */
+        for (i = 0; i < 8; i++)
+                __raw_writel(0, AVIC_NIPRIORITY(i));
 
         /* init architectures chained interrupt handler */
         mxc_register_gpios();