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authorUwe Kleine-König <u.kleine-koenig@pengutronix.de>2010-06-21 11:34:58 -0400
committerUwe Kleine-König <u.kleine-koenig@pengutronix.de>2010-06-30 03:00:48 -0400
commit63ddc5b01681567d10ddb94cb41390c77237cb62 (patch)
tree6e181ea48f1cb9ec48a6227f49e96e41caefe200 /arch/arm/plat-mxc
parent642e466bf405ba558e68353cd4ae6e8ed640b123 (diff)
ARM: imx: dynamically register spi_imx devices (imx25)
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Diffstat (limited to 'arch/arm/plat-mxc')
-rw-r--r--arch/arm/plat-mxc/include/mach/mx25.h8
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index 1ebf33fedaaf..16ac6b6d496f 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -14,6 +14,7 @@
14#define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000) 14#define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000)
15#define MX25_I2C3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x84000) 15#define MX25_I2C3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x84000)
16#define MX25_I2C2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x98000) 16#define MX25_I2C2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x98000)
17#define MX25_CSPI1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa4000)
17#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000) 18#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000)
18 19
19#define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) 20#define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000)
@@ -33,18 +34,23 @@
33#define MX25_UART1_BASE_ADDR 0x43f90000 34#define MX25_UART1_BASE_ADDR 0x43f90000
34#define MX25_UART2_BASE_ADDR 0x43f94000 35#define MX25_UART2_BASE_ADDR 0x43f94000
35 36
37#define MX25_CSPI3_BASE_ADDR 0x50004000
38#define MX25_CSPI2_BASE_ADDR 0x50010000
36#define MX25_FEC_BASE_ADDR 0x50038000 39#define MX25_FEC_BASE_ADDR 0x50038000
37#define MX25_NFC_BASE_ADDR 0xbb000000 40#define MX25_NFC_BASE_ADDR 0xbb000000
38#define MX25_DRYICE_BASE_ADDR 0x53ffc000 41#define MX25_DRYICE_BASE_ADDR 0x53ffc000
39#define MX25_LCDC_BASE_ADDR 0x53fbc000 42#define MX25_LCDC_BASE_ADDR 0x53fbc000
40 43
44#define MX25_INT_CSPI3 0
41#define MX25_INT_I2C1 3 45#define MX25_INT_I2C1 3
42#define MX25_INT_I2C2 4 46#define MX25_INT_I2C2 4
43#define MX25_INT_I2C3 10 47#define MX25_INT_I2C3 10
48#define MX25_INT_CSPI2 13
49#define MX25_INT_CSPI1 14
44#define MX25_INT_DRYICE 25 50#define MX25_INT_DRYICE 25
45#define MX25_INT_FEC 57
46#define MX25_INT_NANDFC 33 51#define MX25_INT_NANDFC 33
47#define MX25_INT_LCDC 39 52#define MX25_INT_LCDC 39
53#define MX25_INT_FEC 57
48 54
49#if defined(IMX_NEEDS_DEPRECATED_SYMBOLS) 55#if defined(IMX_NEEDS_DEPRECATED_SYMBOLS)
50#define UART1_BASE_ADDR MX25_UART1_BASE_ADDR 56#define UART1_BASE_ADDR MX25_UART1_BASE_ADDR