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authorSascha Hauer <s.hauer@pengutronix.de>2010-08-19 08:08:04 -0400
committerUwe Kleine-König <u.kleine-koenig@pengutronix.de>2010-09-27 06:52:58 -0400
commitf2b8901d3efe5e1603c8f6a102b2d5c851c108c6 (patch)
treed6e3ab1c55f591e62e8a06991fde43856d2e04dc /arch/arm/plat-mxc
parentab3d8b5859234d1d60b9592e9e9c5eaa9bb55678 (diff)
ARM: imx: Add EPIT support
The Enhanced Periodic Interrupt Timer (EPIT) is found on newer i.MX SoCs and can be used as an alternative system timer. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Diffstat (limited to 'arch/arm/plat-mxc')
-rw-r--r--arch/arm/plat-mxc/Kconfig12
-rw-r--r--arch/arm/plat-mxc/Makefile1
-rw-r--r--arch/arm/plat-mxc/epit.c242
-rw-r--r--arch/arm/plat-mxc/include/mach/common.h1
4 files changed, 256 insertions, 0 deletions
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 6785db4179b8..95f8d614d4fc 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -92,6 +92,18 @@ config MXC_DEBUG_BOARD
92 data/address de-multiplexing and decode, signal level shift, 92 data/address de-multiplexing and decode, signal level shift,
93 interrupt control and various board functions. 93 interrupt control and various board functions.
94 94
95config HAVE_EPIT
96 bool
97
98config MXC_USE_EPIT
99 bool "Use EPIT instead of GPT"
100 depends on HAVE_EPIT
101 help
102 Use EPIT as the system timer on systems that have it. Normally you
103 don't have a reason to do so as the EPIT has the same features and
104 uses the same clocks as the GPT. Anyway, on some systems the GPT
105 may be in use for other purposes.
106
95config MXC_ULPI 107config MXC_ULPI
96 bool 108 bool
97 109
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 78d405ed8616..bb3443f9751a 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
13obj-$(CONFIG_MXC_PWM) += pwm.o 13obj-$(CONFIG_MXC_PWM) += pwm.o
14obj-$(CONFIG_USB_EHCI_MXC) += ehci.o 14obj-$(CONFIG_USB_EHCI_MXC) += ehci.o
15obj-$(CONFIG_MXC_ULPI) += ulpi.o 15obj-$(CONFIG_MXC_ULPI) += ulpi.o
16obj-$(CONFIG_MXC_USE_EPIT) += epit.o
16obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o 17obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
17obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o 18obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o
18obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o 19obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
diff --git a/arch/arm/plat-mxc/epit.c b/arch/arm/plat-mxc/epit.c
new file mode 100644
index 000000000000..ee9582f4972e
--- /dev/null
+++ b/arch/arm/plat-mxc/epit.c
@@ -0,0 +1,242 @@
1/*
2 * linux/arch/arm/plat-mxc/epit.c
3 *
4 * Copyright (C) 2010 Sascha Hauer <s.hauer@pengutronix.de>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
18 * MA 02110-1301, USA.
19 */
20
21#define EPITCR 0x00
22#define EPITSR 0x04
23#define EPITLR 0x08
24#define EPITCMPR 0x0c
25#define EPITCNR 0x10
26
27#define EPITCR_EN (1 << 0)
28#define EPITCR_ENMOD (1 << 1)
29#define EPITCR_OCIEN (1 << 2)
30#define EPITCR_RLD (1 << 3)
31#define EPITCR_PRESC(x) (((x) & 0xfff) << 4)
32#define EPITCR_SWR (1 << 16)
33#define EPITCR_IOVW (1 << 17)
34#define EPITCR_DBGEN (1 << 18)
35#define EPITCR_WAITEN (1 << 19)
36#define EPITCR_RES (1 << 20)
37#define EPITCR_STOPEN (1 << 21)
38#define EPITCR_OM_DISCON (0 << 22)
39#define EPITCR_OM_TOGGLE (1 << 22)
40#define EPITCR_OM_CLEAR (2 << 22)
41#define EPITCR_OM_SET (3 << 22)
42#define EPITCR_CLKSRC_OFF (0 << 24)
43#define EPITCR_CLKSRC_PERIPHERAL (1 << 24)
44#define EPITCR_CLKSRC_REF_HIGH (1 << 24)
45#define EPITCR_CLKSRC_REF_LOW (3 << 24)
46
47#define EPITSR_OCIF (1 << 0)
48
49#include <linux/interrupt.h>
50#include <linux/irq.h>
51#include <linux/clockchips.h>
52#include <linux/clk.h>
53
54#include <mach/hardware.h>
55#include <asm/mach/time.h>
56#include <mach/common.h>
57
58static struct clock_event_device clockevent_epit;
59static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
60
61static void __iomem *timer_base;
62
63static inline void epit_irq_disable(void)
64{
65 u32 val;
66
67 val = __raw_readl(timer_base + EPITCR);
68 val &= ~EPITCR_OCIEN;
69 __raw_writel(val, timer_base + EPITCR);
70}
71
72static inline void epit_irq_enable(void)
73{
74 u32 val;
75
76 val = __raw_readl(timer_base + EPITCR);
77 val |= EPITCR_OCIEN;
78 __raw_writel(val, timer_base + EPITCR);
79}
80
81static void epit_irq_acknowledge(void)
82{
83 __raw_writel(EPITSR_OCIF, timer_base + EPITSR);
84}
85
86static cycle_t epit_read(struct clocksource *cs)
87{
88 return 0 - __raw_readl(timer_base + EPITCNR);
89}
90
91static struct clocksource clocksource_epit = {
92 .name = "epit",
93 .rating = 200,
94 .read = epit_read,
95 .mask = CLOCKSOURCE_MASK(32),
96 .shift = 20,
97 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
98};
99
100static int __init epit_clocksource_init(struct clk *timer_clk)
101{
102 unsigned int c = clk_get_rate(timer_clk);
103
104 clocksource_epit.mult = clocksource_hz2mult(c,
105 clocksource_epit.shift);
106 clocksource_register(&clocksource_epit);
107
108 return 0;
109}
110
111/* clock event */
112
113static int epit_set_next_event(unsigned long evt,
114 struct clock_event_device *unused)
115{
116 unsigned long tcmp;
117
118 tcmp = __raw_readl(timer_base + EPITCNR);
119
120 __raw_writel(tcmp - evt, timer_base + EPITCMPR);
121
122 return 0;
123}
124
125static void epit_set_mode(enum clock_event_mode mode,
126 struct clock_event_device *evt)
127{
128 unsigned long flags;
129
130 /*
131 * The timer interrupt generation is disabled at least
132 * for enough time to call epit_set_next_event()
133 */
134 local_irq_save(flags);
135
136 /* Disable interrupt in GPT module */
137 epit_irq_disable();
138
139 if (mode != clockevent_mode) {
140 /* Set event time into far-far future */
141
142 /* Clear pending interrupt */
143 epit_irq_acknowledge();
144 }
145
146 /* Remember timer mode */
147 clockevent_mode = mode;
148 local_irq_restore(flags);
149
150 switch (mode) {
151 case CLOCK_EVT_MODE_PERIODIC:
152 printk(KERN_ERR "epit_set_mode: Periodic mode is not "
153 "supported for i.MX EPIT\n");
154 break;
155 case CLOCK_EVT_MODE_ONESHOT:
156 /*
157 * Do not put overhead of interrupt enable/disable into
158 * epit_set_next_event(), the core has about 4 minutes
159 * to call epit_set_next_event() or shutdown clock after
160 * mode switching
161 */
162 local_irq_save(flags);
163 epit_irq_enable();
164 local_irq_restore(flags);
165 break;
166 case CLOCK_EVT_MODE_SHUTDOWN:
167 case CLOCK_EVT_MODE_UNUSED:
168 case CLOCK_EVT_MODE_RESUME:
169 /* Left event sources disabled, no more interrupts appear */
170 break;
171 }
172}
173
174/*
175 * IRQ handler for the timer
176 */
177static irqreturn_t epit_timer_interrupt(int irq, void *dev_id)
178{
179 struct clock_event_device *evt = &clockevent_epit;
180
181 epit_irq_acknowledge();
182
183 evt->event_handler(evt);
184
185 return IRQ_HANDLED;
186}
187
188static struct irqaction epit_timer_irq = {
189 .name = "i.MX EPIT Timer Tick",
190 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
191 .handler = epit_timer_interrupt,
192};
193
194static struct clock_event_device clockevent_epit = {
195 .name = "epit",
196 .features = CLOCK_EVT_FEAT_ONESHOT,
197 .shift = 32,
198 .set_mode = epit_set_mode,
199 .set_next_event = epit_set_next_event,
200 .rating = 200,
201};
202
203static int __init epit_clockevent_init(struct clk *timer_clk)
204{
205 unsigned int c = clk_get_rate(timer_clk);
206
207 clockevent_epit.mult = div_sc(c, NSEC_PER_SEC,
208 clockevent_epit.shift);
209 clockevent_epit.max_delta_ns =
210 clockevent_delta2ns(0xfffffffe, &clockevent_epit);
211 clockevent_epit.min_delta_ns =
212 clockevent_delta2ns(0x800, &clockevent_epit);
213
214 clockevent_epit.cpumask = cpumask_of(0);
215
216 clockevents_register_device(&clockevent_epit);
217
218 return 0;
219}
220
221void __init epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
222{
223 clk_enable(timer_clk);
224
225 timer_base = base;
226
227 /*
228 * Initialise to a known state (all timers off, and timing reset)
229 */
230 __raw_writel(0x0, timer_base + EPITCR);
231
232 __raw_writel(0xffffffff, timer_base + EPITLR);
233 __raw_writel(EPITCR_EN | EPITCR_CLKSRC_REF_HIGH | EPITCR_WAITEN,
234 timer_base + EPITCR);
235
236 /* init and register the timer to the framework */
237 epit_clocksource_init(timer_clk);
238 epit_clockevent_init(timer_clk);
239
240 /* Make irqs happen */
241 setup_irq(irq, &epit_timer_irq);
242}
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 2941472582d2..7a1e1f89ff09 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -32,6 +32,7 @@ extern void mx31_init_irq(void);
32extern void mx35_init_irq(void); 32extern void mx35_init_irq(void);
33extern void mx51_init_irq(void); 33extern void mx51_init_irq(void);
34extern void mxc91231_init_irq(void); 34extern void mxc91231_init_irq(void);
35extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq);
35extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); 36extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int);
36extern int mx1_clocks_init(unsigned long fref); 37extern int mx1_clocks_init(unsigned long fref);
37extern int mx21_clocks_init(unsigned long lref, unsigned long fref); 38extern int mx21_clocks_init(unsigned long lref, unsigned long fref);