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authorSascha Hauer <s.hauer@pengutronix.de>2010-03-18 11:56:30 -0400
committerSascha Hauer <s.hauer@pengutronix.de>2010-03-19 06:05:40 -0400
commit3d1bc8626c7b17facfcb7fb5dee4686f47a1e75d (patch)
treeae6732273dfd063bca549c5bfd8e855c2d886896 /arch/arm/plat-mxc
parent1b6a2b2d0ff2ced5fe608e0b2e13ccd2b7a283e5 (diff)
i.MX51: map TZIC dynamically
This looks cleaner and allows us to call mx51_revision later when we can use ioremap to determine the silicon revision dynamically. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/plat-mxc')
-rw-r--r--arch/arm/plat-mxc/include/mach/mx51.h11
1 files changed, 3 insertions, 8 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
index 771532b6b4a6..f1396bd5621f 100644
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -14,7 +14,7 @@
14 * FB100000 70000000 1M SPBA 0 14 * FB100000 70000000 1M SPBA 0
15 * FB000000 73F00000 1M AIPS 1 15 * FB000000 73F00000 1M AIPS 1
16 * FB200000 83F00000 1M AIPS 2 16 * FB200000 83F00000 1M AIPS 2
17 * FA100000 8FFFC000 16K TZIC (interrupt controller) 17 * 8FFFC000 16K TZIC (interrupt controller)
18 * 90000000 256M CSD0 SDRAM/DDR 18 * 90000000 256M CSD0 SDRAM/DDR
19 * A0000000 256M CSD1 SDRAM/DDR 19 * A0000000 256M CSD1 SDRAM/DDR
20 * B0000000 128M CS0 Flash 20 * B0000000 128M CS0 Flash
@@ -49,9 +49,8 @@
49#define MX51_GPU_BASE_ADDR 0x20000000 49#define MX51_GPU_BASE_ADDR 0x20000000
50#define MX51_GPU2D_BASE_ADDR 0xD0000000 50#define MX51_GPU2D_BASE_ADDR 0xD0000000
51 51
52#define MX51_TZIC_BASE_ADDR 0x8FFFC000 52#define MX51_TZIC_BASE_ADDR_TO1 0x8FFFC000
53#define MX51_TZIC_BASE_ADDR_VIRT 0xFA100000 53#define MX51_TZIC_BASE_ADDR 0xE0000000
54#define MX51_TZIC_SIZE SZ_16K
55 54
56#define MX51_DEBUG_BASE_ADDR 0x60000000 55#define MX51_DEBUG_BASE_ADDR 0x60000000
57#define MX51_DEBUG_BASE_ADDR_VIRT 0xFA200000 56#define MX51_DEBUG_BASE_ADDR_VIRT 0xFA200000
@@ -232,7 +231,6 @@
232#define MX51_IO_ADDRESS(x) \ 231#define MX51_IO_ADDRESS(x) \
233 (void __iomem *) \ 232 (void __iomem *) \
234 (MX51_IS_MODULE(x, IRAM) ? MX51_IRAM_IO_ADDRESS(x) : \ 233 (MX51_IS_MODULE(x, IRAM) ? MX51_IRAM_IO_ADDRESS(x) : \
235 MX51_IS_MODULE(x, TZIC) ? MX51_TZIC_IO_ADDRESS(x) : \
236 MX51_IS_MODULE(x, DEBUG) ? MX51_DEBUG_IO_ADDRESS(x) : \ 234 MX51_IS_MODULE(x, DEBUG) ? MX51_DEBUG_IO_ADDRESS(x) : \
237 MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) : \ 235 MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) : \
238 MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) : \ 236 MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) : \
@@ -246,9 +244,6 @@
246#define MX51_IRAM_IO_ADDRESS(x) \ 244#define MX51_IRAM_IO_ADDRESS(x) \
247 (((x) - MX51_IRAM_BASE_ADDR) + MX51_IRAM_BASE_ADDR_VIRT) 245 (((x) - MX51_IRAM_BASE_ADDR) + MX51_IRAM_BASE_ADDR_VIRT)
248 246
249#define MX51_TZIC_IO_ADDRESS(x) \
250 (((x) - MX51_TZIC_BASE_ADDR) + MX51_TZIC_BASE_ADDR_VIRT)
251
252#define MX51_DEBUG_IO_ADDRESS(x) \ 247#define MX51_DEBUG_IO_ADDRESS(x) \
253 (((x) - MX51_DEBUG_BASE_ADDR) + MX51_DEBUG_BASE_ADDR_VIRT) 248 (((x) - MX51_DEBUG_BASE_ADDR) + MX51_DEBUG_BASE_ADDR_VIRT)
254 249