Merge branch 'next/devel' of git://git.linaro.org/people/arnd/arm-soc

* 'next/devel' of git://git.linaro.org/people/arnd/arm-soc: (50 commits)
  ARM: tegra: update defconfig
  arm/tegra: Harmony: Configure PMC for low-level interrupts
  arm/tegra: device tree support for ventana board
  arm/tegra: add support for ventana pinmuxing
  arm/tegra: prepare Seaboard pinmux code for derived boards
  arm/tegra: pinmux: ioremap registers
  gpio/tegra: Convert to a platform device
  arm/tegra: Convert pinmux driver to a platform device
  arm/dt: Tegra: Add pinmux node to tegra20.dtsi
  arm/tegra: Prep boards for gpio/pinmux conversion to pdevs
  ARM: mx5: fix clock usage for suspend
  ARM i.MX entry-macro.S: remove now unused code
  ARM i.MX boards: use CONFIG_MULTI_IRQ_HANDLER
  ARM i.MX tzic: add handle_irq function
  ARM i.MX avic: add handle_irq function
  ARM: mx25: Add the missing IIM base definition
  ARM i.MX avic: convert to use generic irq chip
  mx31moboard: Add poweroff support
  ARM: mach-qong: Add watchdog support
  ARM: davinci: AM18x: Add wl1271/wlan support
  ...

Fix up conflicts in:
	arch/arm/mach-at91/at91sam9g45.c
	arch/arm/mach-mx5/devices-imx53.h
	arch/arm/plat-mxc/include/mach/memory.h

12 files changed, 154 insertions, 140 deletions

diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 4c8fdbcc9467..4bdc975581eb 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -4,50 +4,31 @@ source "arch/arm/plat-mxc/devices/Kconfig"
 
 menu "Freescale MXC Implementations"
 
-config ARCH_MX50_SUPPORTED
-        bool
-
-config ARCH_MX53_SUPPORTED
-        bool
-
 choice
         prompt "Freescale CPU family:"
         default ARCH_MX3
 
-config ARCH_MX1
-        bool "MX1-based"
-        help
-          This enables support for systems based on the Freescale i.MX1 family
-
-config ARCH_MX2
-        bool "MX2-based"
-        help
-          This enables support for systems based on the Freescale i.MX2 family
-
-config ARCH_MX25
-        bool "MX25-based"
+config ARCH_IMX_V4_V5
+        bool "i.MX1, i.MX21, i.MX25, i.MX27"
+        select AUTO_ZRELADDR
+        select ARM_PATCH_PHYS_VIRT
         help
-          This enables support for systems based on the Freescale i.MX25 family
+          This enables support for systems based on the Freescale i.MX ARMv4
+          and ARMv5 SoCs
 
 config ARCH_MX3
         bool "MX3-based"
         help
           This enables support for systems based on the Freescale i.MX3 family
 
-config ARCH_MX503
-        bool "i.MX50 + i.MX53"
-        select ARCH_MX50_SUPPORTED
-        select ARCH_MX53_SUPPORTED
+config ARCH_MX5
+        bool "i.MX50, i.MX51, i.MX53"
+        select AUTO_ZRELADDR
+        select ARM_PATCH_PHYS_VIRT
         help
           This enables support for machines using Freescale's i.MX50 and i.MX53
           processors.
 
-config ARCH_MX51
-        bool "i.MX51"
-        select ARCH_MX51_SUPPORTED
-        help
-          This enables support for systems based on the Freescale i.MX51 family
-
 endchoice
 
 source "arch/arm/mach-imx/Kconfig"
diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c
index 55d2534ec727..8875fb415f68 100644
--- a/arch/arm/plat-mxc/avic.c
+++ b/arch/arm/plat-mxc/avic.c
@@ -50,6 +50,8 @@
 
 void __iomem *avic_base;
 
+static u32 avic_saved_mask_reg[2];
+
 #ifdef CONFIG_MXC_IRQ_PRIOR
 static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
 {
@@ -90,24 +92,8 @@ static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
 }
 #endif /* CONFIG_FIQ */
 
-/* Disable interrupt number "irq" in the AVIC */
-static void mxc_mask_irq(struct irq_data *d)
-{
-        __raw_writel(d->irq, avic_base + AVIC_INTDISNUM);
-}
 
-/* Enable interrupt number "irq" in the AVIC */
-static void mxc_unmask_irq(struct irq_data *d)
-{
-        __raw_writel(d->irq, avic_base + AVIC_INTENNUM);
-}
-
-static struct mxc_irq_chip mxc_avic_chip = {
-        .base = {
-                .irq_ack = mxc_mask_irq,
-                .irq_mask = mxc_mask_irq,
-                .irq_unmask = mxc_unmask_irq,
-        },
+static struct mxc_extra_irq avic_extra_irq = {
 #ifdef CONFIG_MXC_IRQ_PRIOR
         .set_priority = avic_irq_set_priority,
 #endif
@@ -116,6 +102,68 @@ static struct mxc_irq_chip mxc_avic_chip = {
 #endif
 };
 
+#ifdef CONFIG_PM
+static void avic_irq_suspend(struct irq_data *d)
+{
+        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+        struct irq_chip_type *ct = gc->chip_types;
+        int idx = gc->irq_base >> 5;
+
+        avic_saved_mask_reg[idx] = __raw_readl(avic_base + ct->regs.mask);
+        __raw_writel(gc->wake_active, avic_base + ct->regs.mask);
+}
+
+static void avic_irq_resume(struct irq_data *d)
+{
+        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+        struct irq_chip_type *ct = gc->chip_types;
+        int idx = gc->irq_base >> 5;
+
+        __raw_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);
+}
+
+#else
+#define avic_irq_suspend NULL
+#define avic_irq_resume NULL
+#endif
+
+static __init void avic_init_gc(unsigned int irq_start)
+{
+        struct irq_chip_generic *gc;
+        struct irq_chip_type *ct;
+        int idx = irq_start >> 5;
+
+        gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base,
+                                    handle_level_irq);
+        gc->private = &avic_extra_irq;
+        gc->wake_enabled = IRQ_MSK(32);
+
+        ct = gc->chip_types;
+        ct->chip.irq_mask = irq_gc_mask_clr_bit;
+        ct->chip.irq_unmask = irq_gc_mask_set_bit;
+        ct->chip.irq_ack = irq_gc_mask_clr_bit;
+        ct->chip.irq_set_wake = irq_gc_set_wake;
+        ct->chip.irq_suspend = avic_irq_suspend;
+        ct->chip.irq_resume = avic_irq_resume;
+        ct->regs.mask = !idx ? AVIC_INTENABLEL : AVIC_INTENABLEH;
+        ct->regs.ack = ct->regs.mask;
+
+        irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
+}
+
+asmlinkage void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
+{
+        u32 nivector;
+
+        do {
+                nivector = __raw_readl(avic_base + AVIC_NIVECSR) >> 16;
+                if (nivector == 0xffff)
+                        break;
+
+                handle_IRQ(nivector, regs);
+        } while (1);
+}
+
 /*
  * This function initializes the AVIC hardware and disables all the
  * interrupts. It registers the interrupt enable and disable functions
@@ -140,11 +188,9 @@ void __init mxc_init_irq(void __iomem *irqbase)
         /* all IRQ no FIQ */
         __raw_writel(0, avic_base + AVIC_INTTYPEH);
         __raw_writel(0, avic_base + AVIC_INTTYPEL);
-        for (i = 0; i < AVIC_NUM_IRQS; i++) {
-                irq_set_chip_and_handler(i, &mxc_avic_chip.base,
-                                         handle_level_irq);
-                set_irq_flags(i, IRQF_VALID);
-        }
+
+        for (i = 0; i < AVIC_NUM_IRQS; i += 32)
+                avic_init_gc(i);
 
         /* Set default priority value (0) for all IRQ's */
         for (i = 0; i < 8; i++)
@@ -157,4 +203,3 @@ void __init mxc_init_irq(void __iomem *irqbase)
 
         printk(KERN_INFO "MXC IRQ initialized\n");
 }
-
diff --git a/arch/arm/plat-mxc/cpu.c b/arch/arm/plat-mxc/cpu.c
index 386e0d52cf58..f5b7e0fa237f 100644
--- a/arch/arm/plat-mxc/cpu.c
+++ b/arch/arm/plat-mxc/cpu.c
@@ -1,5 +1,6 @@
 
 #include <linux/module.h>
+#include <mach/hardware.h>
 
 unsigned int __mxc_cpu_type;
 EXPORT_SYMBOL(__mxc_cpu_type);
@@ -9,3 +10,11 @@ void mxc_set_cpu_type(unsigned int type)
         __mxc_cpu_type = type;
 }
 
+void imx_print_silicon_rev(const char *cpu, int srev)
+{
+        if (srev == IMX_CHIP_REVISION_UNKNOWN)
+                pr_info("CPU identified as %s, unknown revision\n", cpu);
+        else
+                pr_info("CPU identified as %s, silicon rev %d.%d\n",
+                                cpu, (srev >> 4) & 0xf, srev & 0xf);
+}
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index d7149d1bd32c..ace4bb550edc 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -82,4 +82,19 @@ enum mxc_cpu_pwr_mode {
 
 extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
 extern void (*imx_idle)(void);
+extern void imx_print_silicon_rev(const char *cpu, int srev);
+
+void avic_handle_irq(struct pt_regs *);
+void tzic_handle_irq(struct pt_regs *);
+
+#define imx1_handle_irq avic_handle_irq
+#define imx21_handle_irq avic_handle_irq
+#define imx25_handle_irq avic_handle_irq
+#define imx27_handle_irq avic_handle_irq
+#define imx31_handle_irq avic_handle_irq
+#define imx35_handle_irq avic_handle_irq
+#define imx50_handle_irq tzic_handle_irq
+#define imx51_handle_irq tzic_handle_irq
+#define imx53_handle_irq tzic_handle_irq
+
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S
index 066d464d322d..842fbcb0d6cc 100644
--- a/arch/arm/plat-mxc/include/mach/entry-macro.S
+++ b/arch/arm/plat-mxc/include/mach/entry-macro.S
@@ -9,72 +9,16 @@
  * published by the Free Software Foundation.
  */
 
-#include <mach/hardware.h>
+/* Unused, we use CONFIG_MULTI_IRQ_HANDLER */
 
-#define AVIC_NIMASK     0x04
-
-        @ this macro disables fast irq (not implemented)
         .macro  disable_fiq
         .endm
 
         .macro  get_irqnr_preamble, base, tmp
-#ifndef CONFIG_MXC_TZIC
-        ldr     \base, =avic_base
-        ldr     \base, [\base]
-#ifdef CONFIG_MXC_IRQ_PRIOR
-        ldr     r4, [\base, #AVIC_NIMASK]
-#endif
-#elif defined CONFIG_MXC_TZIC
-        ldr     \base, =tzic_base
-        ldr     \base, [\base]
-#endif /* CONFIG_MXC_TZIC */
         .endm
 
         .macro  arch_ret_to_user, tmp1, tmp2
         .endm
 
-        @ this macro checks which interrupt occurred
-        @ and returns its number in irqnr
-        @ and returns if an interrupt occurred in irqstat
         .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-#ifndef CONFIG_MXC_TZIC
-        @ Load offset & priority of the highest priority
-        @ interrupt pending from AVIC_NIVECSR
-        ldr     \irqstat, [\base, #0x40]
-        @ Shift to get the decoded IRQ number, using ASR so
-        @ 'no interrupt pending' becomes 0xffffffff
-        mov     \irqnr, \irqstat, asr #16
-        @ set zero flag if IRQ + 1 == 0
-        adds    \tmp, \irqnr, #1
-#ifdef CONFIG_MXC_IRQ_PRIOR
-        bicne   \tmp, \irqstat, #0xFFFFFFE0
-        strne   \tmp, [\base, #AVIC_NIMASK]
-        streq   r4, [\base, #AVIC_NIMASK]
-#endif
-#elif defined CONFIG_MXC_TZIC
-        @ Load offset & priority of the highest priority
-        @ interrupt pending.
-        @ 0x080 is INTSEC0 register
-        @ 0xD80 is HIPND0 register
-        mov     \irqnr, #0
-1000:   add     \irqstat, \base, \irqnr, lsr #3
-        ldr     \tmp, [\irqstat, #0xd80]
-        ldr     \irqstat, [\irqstat, #0x080]
-        ands    \tmp, \tmp, \irqstat
-        bne     1001f
-        add     \irqnr, \irqnr, #32
-        cmp     \irqnr, #128
-        blo     1000b
-        b       2001f
-1001:   mov     \irqstat, #1
-1002:   tst     \tmp, \irqstat
-        bne     2002f
-        movs    \tmp, \tmp, lsr #1
-        addne   \irqnr, \irqnr, #1
-        bne     1002b
-2001:
-        mov  \irqnr, #0
-2002:
-        movs \irqnr, \irqnr
-#endif
         .endm
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index c92f0b1f216f..63f22a009a65 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -735,6 +735,7 @@ enum iomux_pins {
 #define MX31_PIN_KEY_COL5_KEY_COL5      IOMUX_MODE(MX31_PIN_KEY_COL5, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_KEY_COL6_KEY_COL6      IOMUX_MODE(MX31_PIN_KEY_COL6, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_KEY_COL7_KEY_COL7      IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_WATCHDOG_RST__WATCHDOG_RST     IOMUX_MODE(MX31_PIN_WATCHDOG_RST, IOMUX_CONFIG_FUNC)
 
 
 /*
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index 087cd7ac8d52..ccebf5ba12f0 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -41,6 +41,7 @@
 #define MX25_SSI2_BASE_ADDR             0x50014000
 #define MX25_SSI1_BASE_ADDR             0x50034000
 #define MX25_NFC_BASE_ADDR              0xbb000000
+#define MX25_IIM_BASE_ADDR              0x53ff0000
 #define MX25_DRYICE_BASE_ADDR           0x53ffc000
 #define MX25_ESDHC1_BASE_ADDR           0x53fb4000
 #define MX25_ESDHC2_BASE_ADDR           0x53fb8000
@@ -104,4 +105,8 @@
 #define MX25_DMA_REQ_SSI1_RX0   28
 #define MX25_DMA_REQ_SSI1_TX0   29
 
+#ifndef __ASSEMBLY__
+extern int mx25_revision(void);
+#endif
+
 #endif /* ifndef __MACH_MX25_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
index 388a407d72d6..30dbf424583e 100644
--- a/arch/arm/plat-mxc/include/mach/mx3x.h
+++ b/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -187,22 +187,8 @@
 /* Mandatory defines used globally */
 
 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
-
-extern unsigned int mx31_cpu_rev;
-extern void mx31_read_cpu_rev(void);
-
-static inline int mx31_revision(void)
-{
-        return mx31_cpu_rev;
-}
-
-extern unsigned int mx35_cpu_rev;
-extern void mx35_read_cpu_rev(void);
-
-static inline int mx35_revision(void)
-{
-        return mx35_cpu_rev;
-}
+extern int mx35_revision(void);
+extern int mx31_revision(void);
 #endif
 
 #endif /* ifndef __MACH_MX3x_H__ */
diff --git a/arch/arm/plat-mxc/irq-common.c b/arch/arm/plat-mxc/irq-common.c
index 96953e2e4f11..b6e11458e5ae 100644
--- a/arch/arm/plat-mxc/irq-common.c
+++ b/arch/arm/plat-mxc/irq-common.c
@@ -23,17 +23,17 @@
 
 int imx_irq_set_priority(unsigned char irq, unsigned char prio)
 {
-        struct mxc_irq_chip *chip;
-        struct irq_chip *base;
+        struct irq_chip_generic *gc;
+        struct mxc_extra_irq *exirq;
         int ret;
 
         ret = -ENOSYS;
 
-        base = irq_get_chip(irq);
-        if (base) {
-                chip = container_of(base, struct mxc_irq_chip, base);
-                if (chip->set_priority)
-                        ret = chip->set_priority(irq, prio);
+        gc = irq_get_chip_data(irq);
+        if (gc && gc->private) {
+                exirq = gc->private;
+                if (exirq->set_priority)
+                        ret = exirq->set_priority(irq, prio);
         }
 
         return ret;
@@ -43,15 +43,16 @@ EXPORT_SYMBOL(imx_irq_set_priority);
 int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
 {
         struct irq_chip_generic *gc;
-        int (*set_irq_fiq)(unsigned int, unsigned int);
+        struct mxc_extra_irq *exirq;
         int ret;
 
         ret = -ENOSYS;
 
         gc = irq_get_chip_data(irq);
         if (gc && gc->private) {
-                set_irq_fiq = gc->private;
-                ret = set_irq_fiq(irq, type);
+                exirq = gc->private;
+                if (exirq->set_irq_fiq)
+                        ret = exirq->set_irq_fiq(irq, type);
         }
 
         return ret;
diff --git a/arch/arm/plat-mxc/irq-common.h b/arch/arm/plat-mxc/irq-common.h
index 7203543fb1b3..6ccb3a14c693 100644
--- a/arch/arm/plat-mxc/irq-common.h
+++ b/arch/arm/plat-mxc/irq-common.h
@@ -19,9 +19,8 @@
 #ifndef __PLAT_MXC_IRQ_COMMON_H__
 #define __PLAT_MXC_IRQ_COMMON_H__
 
-struct mxc_irq_chip
+struct mxc_extra_irq
 {
-        struct irq_chip base;
         int (*set_priority)(unsigned char irq, unsigned char prio);
         int (*set_irq_fiq)(unsigned int irq, unsigned int type);
 };
diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c
index 761c3c940a68..42d74ea59084 100644
--- a/arch/arm/plat-mxc/pwm.c
+++ b/arch/arm/plat-mxc/pwm.c
@@ -57,7 +57,7 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
         if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
                 return -EINVAL;
 
-        if (cpu_is_mx27() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51()) {
+        if (!(cpu_is_mx1() || cpu_is_mx21())) {
                 unsigned long long c;
                 unsigned long period_cycles, duty_cycles, prescale;
                 u32 cr;
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index f257fccdc394..e993a184189a 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -42,7 +42,7 @@
 #define TZIC_SRCCLAR0   0x0280  /* Source Clear Register 0 */
 #define TZIC_PRIORITY0  0x0400  /* Priority Register 0 */
 #define TZIC_PND0       0x0D00  /* Pending Register 0 */
-#define TZIC_HIPND0     0x0D80  /* High Priority Pending Register */
+#define TZIC_HIPND(i)   (0x0D80+ ((i) << 2))    /* High Priority Pending Register */
 #define TZIC_WAKEUP0(i) (0x0E00 + ((i) << 2))   /* Wakeup Config Register */
 #define TZIC_SWINT      0x0F00  /* Software Interrupt Rigger Register */
 #define TZIC_ID0        0x0FD0  /* Indentification Register 0 */
@@ -74,6 +74,12 @@ static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
 
 static unsigned int *wakeup_intr[4];
 
+static struct mxc_extra_irq tzic_extra_irq = {
+#ifdef CONFIG_FIQ
+        .set_irq_fiq = tzic_set_irq_fiq,
+#endif
+};
+
 static __init void tzic_init_gc(unsigned int irq_start)
 {
         struct irq_chip_generic *gc;
@@ -82,7 +88,7 @@ static __init void tzic_init_gc(unsigned int irq_start)
 
         gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base,
                                     handle_level_irq);
-        gc->private = tzic_set_irq_fiq;
+        gc->private = &tzic_extra_irq;
         gc->wake_enabled = IRQ_MSK(32);
         wakeup_intr[idx] = &gc->wake_active;
 
@@ -96,6 +102,28 @@ static __init void tzic_init_gc(unsigned int irq_start)
         irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
 }
 
+asmlinkage void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
+{
+        u32 stat;
+        int i, irqofs, handled;
+
+        do {
+                handled = 0;
+
+                for (i = 0; i < 4; i++) {
+                        stat = __raw_readl(tzic_base + TZIC_HIPND(i)) &
+                                __raw_readl(tzic_base + TZIC_INTSEC0(i));
+
+                        while (stat) {
+                                handled = 1;
+                                irqofs = fls(stat) - 1;
+                                handle_IRQ(irqofs + i * 32, regs);
+                                stat &= ~(1 << irqofs);
+                        }
+                }
+        } while (handled);
+}
+
 /*
  * This function initializes the TZIC hardware and disables all the
  * interrupts. It registers the interrupt enable and disable functions