aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/plat-mxc
diff options
context:
space:
mode:
authorUwe Kleine-König <u.kleine-koenig@pengutronix.de>2009-11-10 04:14:34 -0500
committerSascha Hauer <s.hauer@pengutronix.de>2009-11-18 04:40:28 -0500
commit104071b6dcc66cd66db83231fd3bd58cd63e680d (patch)
treef0d75b596df31bbab7ca42b3d42057538fb65723 /arch/arm/plat-mxc
parent4dc7be72b5c9d33669cb2b68d16c7588fb36d8df (diff)
imx: reorder mx2x.h
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Diffstat (limited to 'arch/arm/plat-mxc')
-rw-r--r--arch/arm/plat-mxc/include/mach/mx2x.h138
1 files changed, 69 insertions, 69 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h
index db5d921e0fe6..c0df87f6c904 100644
--- a/arch/arm/plat-mxc/include/mach/mx2x.h
+++ b/arch/arm/plat-mxc/include/mach/mx2x.h
@@ -105,78 +105,78 @@
105 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) 105 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
106 106
107/* fixed interrupt numbers */ 107/* fixed interrupt numbers */
108#define MXC_INT_LCDC 61
109#define MXC_INT_SLCDC 60
110#define MXC_INT_EMMAPP 52
111#define MXC_INT_EMMAPRP 51
112#define MXC_INT_DMACH15 47
113#define MXC_INT_DMACH14 46
114#define MXC_INT_DMACH13 45
115#define MXC_INT_DMACH12 44
116#define MXC_INT_DMACH11 43
117#define MXC_INT_DMACH10 42
118#define MXC_INT_DMACH9 41
119#define MXC_INT_DMACH8 40
120#define MXC_INT_DMACH7 39
121#define MXC_INT_DMACH6 38
122#define MXC_INT_DMACH5 37
123#define MXC_INT_DMACH4 36
124#define MXC_INT_DMACH3 35
125#define MXC_INT_DMACH2 34
126#define MXC_INT_DMACH1 33
127#define MXC_INT_DMACH0 32
128#define MXC_INT_CSI 31
129#define MXC_INT_NANDFC 29
130#define MXC_INT_PCMCIA 28
131#define MXC_INT_WDOG 27
132#define MXC_INT_GPT1 26
133#define MXC_INT_GPT2 25
134#define MXC_INT_GPT3 24
135#define MXC_INT_GPT INT_GPT1
136#define MXC_INT_PWM 23
137#define MXC_INT_RTC 22
138#define MXC_INT_KPP 21
139#define MXC_INT_UART1 20
140#define MXC_INT_UART2 19
141#define MXC_INT_UART3 18
142#define MXC_INT_UART4 17
143#define MXC_INT_CSPI1 16
144#define MXC_INT_CSPI2 15
145#define MXC_INT_SSI1 14
146#define MXC_INT_SSI2 13
147#define MXC_INT_I2C 12
148#define MXC_INT_SDHC1 11
149#define MXC_INT_SDHC2 10
150#define MXC_INT_GPIO 8
151#define MXC_INT_CSPI3 6 108#define MXC_INT_CSPI3 6
109#define MXC_INT_GPIO 8
110#define MXC_INT_SDHC2 10
111#define MXC_INT_SDHC1 11
112#define MXC_INT_I2C 12
113#define MXC_INT_SSI2 13
114#define MXC_INT_SSI1 14
115#define MXC_INT_CSPI2 15
116#define MXC_INT_CSPI1 16
117#define MXC_INT_UART4 17
118#define MXC_INT_UART3 18
119#define MXC_INT_UART2 19
120#define MXC_INT_UART1 20
121#define MXC_INT_KPP 21
122#define MXC_INT_RTC 22
123#define MXC_INT_PWM 23
124#define MXC_INT_GPT INT_GPT1
125#define MXC_INT_GPT3 24
126#define MXC_INT_GPT2 25
127#define MXC_INT_GPT1 26
128#define MXC_INT_WDOG 27
129#define MXC_INT_PCMCIA 28
130#define MXC_INT_NANDFC 29
131#define MXC_INT_CSI 31
132#define MXC_INT_DMACH0 32
133#define MXC_INT_DMACH1 33
134#define MXC_INT_DMACH2 34
135#define MXC_INT_DMACH3 35
136#define MXC_INT_DMACH4 36
137#define MXC_INT_DMACH5 37
138#define MXC_INT_DMACH6 38
139#define MXC_INT_DMACH7 39
140#define MXC_INT_DMACH8 40
141#define MXC_INT_DMACH9 41
142#define MXC_INT_DMACH10 42
143#define MXC_INT_DMACH11 43
144#define MXC_INT_DMACH12 44
145#define MXC_INT_DMACH13 45
146#define MXC_INT_DMACH14 46
147#define MXC_INT_DMACH15 47
148#define MXC_INT_EMMAPRP 51
149#define MXC_INT_EMMAPP 52
150#define MXC_INT_SLCDC 60
151#define MXC_INT_LCDC 61
152 152
153/* fixed DMA request numbers */ 153/* fixed DMA request numbers */
154#define DMA_REQ_CSI_RX 31
155#define DMA_REQ_CSI_STAT 30
156#define DMA_REQ_UART1_TX 27
157#define DMA_REQ_UART1_RX 26
158#define DMA_REQ_UART2_TX 25
159#define DMA_REQ_UART2_RX 24
160#define DMA_REQ_UART3_TX 23
161#define DMA_REQ_UART3_RX 22
162#define DMA_REQ_UART4_TX 21
163#define DMA_REQ_UART4_RX 20
164#define DMA_REQ_CSPI1_TX 19
165#define DMA_REQ_CSPI1_RX 18
166#define DMA_REQ_CSPI2_TX 17
167#define DMA_REQ_CSPI2_RX 16
168#define DMA_REQ_SSI1_TX1 15
169#define DMA_REQ_SSI1_RX1 14
170#define DMA_REQ_SSI1_TX0 13
171#define DMA_REQ_SSI1_RX0 12
172#define DMA_REQ_SSI2_TX1 11
173#define DMA_REQ_SSI2_RX1 10
174#define DMA_REQ_SSI2_TX0 9
175#define DMA_REQ_SSI2_RX0 8
176#define DMA_REQ_SDHC1 7
177#define DMA_REQ_SDHC2 6
178#define DMA_REQ_EXT 3
179#define DMA_REQ_CSPI3_TX 2
180#define DMA_REQ_CSPI3_RX 1 154#define DMA_REQ_CSPI3_RX 1
155#define DMA_REQ_CSPI3_TX 2
156#define DMA_REQ_EXT 3
157#define DMA_REQ_SDHC2 6
158#define DMA_REQ_SDHC1 7
159#define DMA_REQ_SSI2_RX0 8
160#define DMA_REQ_SSI2_TX0 9
161#define DMA_REQ_SSI2_RX1 10
162#define DMA_REQ_SSI2_TX1 11
163#define DMA_REQ_SSI1_RX0 12
164#define DMA_REQ_SSI1_TX0 13
165#define DMA_REQ_SSI1_RX1 14
166#define DMA_REQ_SSI1_TX1 15
167#define DMA_REQ_CSPI2_RX 16
168#define DMA_REQ_CSPI2_TX 17
169#define DMA_REQ_CSPI1_RX 18
170#define DMA_REQ_CSPI1_TX 19
171#define DMA_REQ_UART4_RX 20
172#define DMA_REQ_UART4_TX 21
173#define DMA_REQ_UART3_RX 22
174#define DMA_REQ_UART3_TX 23
175#define DMA_REQ_UART2_RX 24
176#define DMA_REQ_UART2_TX 25
177#define DMA_REQ_UART1_RX 26
178#define DMA_REQ_UART1_TX 27
179#define DMA_REQ_CSI_STAT 30
180#define DMA_REQ_CSI_RX 31
181 181
182#endif /* __ASM_ARCH_MXC_MX2x_H__ */ 182#endif /* __ASM_ARCH_MXC_MX2x_H__ */