diff options
author | Uwe Kleine-König <u.kleine-koenig@pengutronix.de> | 2009-11-12 15:43:39 -0500 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2009-11-18 04:41:17 -0500 |
commit | 4f683a046cb45f74610fb790e6affa7604636a9f (patch) | |
tree | abffcf701821af103f7d49bc2018dabde76ca82d /arch/arm/plat-mxc | |
parent | e4d0f7c71d60f7a783edd6dcc97423fcc9973aaf (diff) |
imx: add namespace prefixes for symbols in mx31.h
The old names are still defined using the new names.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Diffstat (limited to 'arch/arm/plat-mxc')
-rw-r--r-- | arch/arm/plat-mxc/include/mach/mx31.h | 94 |
1 files changed, 62 insertions, 32 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index 14ac0dcc82f4..a4d6901755c1 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h | |||
@@ -1,45 +1,75 @@ | |||
1 | /* | 1 | /* |
2 | * IRAM | 2 | * IRAM |
3 | */ | 3 | */ |
4 | #define MX31_IRAM_BASE_ADDR 0x1FFC0000 /* internal ram */ | 4 | #define MX31_IRAM_BASE_ADDR 0x1ffc0000 /* internal ram */ |
5 | #define MX31_IRAM_SIZE SZ_16K | 5 | #define MX31_IRAM_SIZE SZ_16K |
6 | 6 | ||
7 | #define MX31_OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) | 7 | #define MX31_OTG_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x88000) |
8 | #define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) | 8 | #define MX31_ATA_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x8c000) |
9 | #define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) | 9 | #define MX31_UART4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xb0000) |
10 | #define UART5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) | 10 | #define MX31_UART5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xb4000) |
11 | 11 | ||
12 | #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) | 12 | #define MX31_MMC_SDHC1_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x04000) |
13 | #define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) | 13 | #define MX31_MMC_SDHC2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x08000) |
14 | #define SIM1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00018000) | 14 | #define MX31_SIM1_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x18000) |
15 | #define IIM_BASE_ADDR (SPBA0_BASE_ADDR + 0x0001C000) | 15 | #define MX31_IIM_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x1c000) |
16 | 16 | ||
17 | #define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) | 17 | #define MX31_CSPI3_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x84000) |
18 | #define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008C000) | 18 | #define MX31_FIRI_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x8c000) |
19 | #define SCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AE000) | 19 | #define MX31_SCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xae000) |
20 | #define SMN_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AF000) | 20 | #define MX31_SMN_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xaf000) |
21 | #define MPEG4_ENC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) | 21 | #define MX31_MPEG4_ENC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc8000) |
22 | 22 | ||
23 | #define MX31_NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000) | 23 | #define MX31_NFC_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x0000) |
24 | 24 | ||
25 | #define MXC_INT_MPEG4_ENCODER 5 | 25 | #define MX31_INT_MPEG4_ENCODER 5 |
26 | #define MXC_INT_FIRI 7 | 26 | #define MX31_INT_FIRI 7 |
27 | #define MX31_INT_MMC_SDHC2 8 | 27 | #define MX31_INT_MMC_SDHC2 8 |
28 | #define MXC_INT_MMC_SDHC1 9 | 28 | #define MX31_INT_MMC_SDHC1 9 |
29 | #define MX31_INT_SSI2 11 | 29 | #define MX31_INT_SSI2 11 |
30 | #define MX31_INT_SSI1 12 | 30 | #define MX31_INT_SSI1 12 |
31 | #define MXC_INT_MBX 16 | 31 | #define MX31_INT_MBX 16 |
32 | #define MXC_INT_CSPI3 17 | 32 | #define MX31_INT_CSPI3 17 |
33 | #define MXC_INT_SIM2 20 | 33 | #define MX31_INT_SIM2 20 |
34 | #define MXC_INT_SIM1 21 | 34 | #define MX31_INT_SIM1 21 |
35 | #define MXC_INT_CCM_DVFS 31 | 35 | #define MX31_INT_CCM_DVFS 31 |
36 | #define MXC_INT_USB1 35 | 36 | #define MX31_INT_USB1 35 |
37 | #define MXC_INT_USB2 36 | 37 | #define MX31_INT_USB2 36 |
38 | #define MXC_INT_USB3 37 | 38 | #define MX31_INT_USB3 37 |
39 | #define MXC_INT_USB4 38 | 39 | #define MX31_INT_USB4 38 |
40 | #define MXC_INT_MSHC2 40 | 40 | #define MX31_INT_MSHC2 40 |
41 | #define MXC_INT_UART4 46 | 41 | #define MX31_INT_UART4 46 |
42 | #define MXC_INT_UART5 47 | 42 | #define MX31_INT_UART5 47 |
43 | #define MXC_INT_CCM 53 | 43 | #define MX31_INT_CCM 53 |
44 | #define MXC_INT_PCMCIA 54 | 44 | #define MX31_INT_PCMCIA 54 |
45 | 45 | ||
46 | /* these should go away */ | ||
47 | #define ATA_BASE_ADDR MX31_ATA_BASE_ADDR | ||
48 | #define UART4_BASE_ADDR MX31_UART4_BASE_ADDR | ||
49 | #define UART5_BASE_ADDR MX31_UART5_BASE_ADDR | ||
50 | #define MMC_SDHC1_BASE_ADDR MX31_MMC_SDHC1_BASE_ADDR | ||
51 | #define MMC_SDHC2_BASE_ADDR MX31_MMC_SDHC2_BASE_ADDR | ||
52 | #define SIM1_BASE_ADDR MX31_SIM1_BASE_ADDR | ||
53 | #define IIM_BASE_ADDR MX31_IIM_BASE_ADDR | ||
54 | #define CSPI3_BASE_ADDR MX31_CSPI3_BASE_ADDR | ||
55 | #define FIRI_BASE_ADDR MX31_FIRI_BASE_ADDR | ||
56 | #define SCM_BASE_ADDR MX31_SCM_BASE_ADDR | ||
57 | #define SMN_BASE_ADDR MX31_SMN_BASE_ADDR | ||
58 | #define MPEG4_ENC_BASE_ADDR MX31_MPEG4_ENC_BASE_ADDR | ||
59 | #define MXC_INT_MPEG4_ENCODER MX31_INT_MPEG4_ENCODER | ||
60 | #define MXC_INT_FIRI MX31_INT_FIRI | ||
61 | #define MXC_INT_MMC_SDHC1 MX31_INT_MMC_SDHC1 | ||
62 | #define MXC_INT_MBX MX31_INT_MBX | ||
63 | #define MXC_INT_CSPI3 MX31_INT_CSPI3 | ||
64 | #define MXC_INT_SIM2 MX31_INT_SIM2 | ||
65 | #define MXC_INT_SIM1 MX31_INT_SIM1 | ||
66 | #define MXC_INT_CCM_DVFS MX31_INT_CCM_DVFS | ||
67 | #define MXC_INT_USB1 MX31_INT_USB1 | ||
68 | #define MXC_INT_USB2 MX31_INT_USB2 | ||
69 | #define MXC_INT_USB3 MX31_INT_USB3 | ||
70 | #define MXC_INT_USB4 MX31_INT_USB4 | ||
71 | #define MXC_INT_MSHC2 MX31_INT_MSHC2 | ||
72 | #define MXC_INT_UART4 MX31_INT_UART4 | ||
73 | #define MXC_INT_UART5 MX31_INT_UART5 | ||
74 | #define MXC_INT_CCM MX31_INT_CCM | ||
75 | #define MXC_INT_PCMCIA MX31_INT_PCMCIA | ||