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authorUwe Kleine-König <u.kleine-koenig@pengutronix.de>2009-11-10 05:34:22 -0500
committerSascha Hauer <s.hauer@pengutronix.de>2009-11-18 04:40:50 -0500
commitb9fc90a48a3d1794443e095d8585dcaeafb2195f (patch)
treec9434b60d90dd478d110a60a5521dfb6b662e386 /arch/arm/plat-mxc
parente676756fa43e04166111e4729c62bb4fdf477255 (diff)
imx: add namespace prefixes for symbols in mx2x.h
The old names are still defined using the new names. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Diffstat (limited to 'arch/arm/plat-mxc')
-rw-r--r--arch/arm/plat-mxc/include/mach/mx2x.h339
1 files changed, 224 insertions, 115 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h
index c0df87f6c904..1766c7c91842 100644
--- a/arch/arm/plat-mxc/include/mach/mx2x.h
+++ b/arch/arm/plat-mxc/include/mach/mx2x.h
@@ -26,50 +26,48 @@
26/* The following addresses are common between i.MX21 and i.MX27 */ 26/* The following addresses are common between i.MX21 and i.MX27 */
27 27
28/* Register offests */ 28/* Register offests */
29#define AIPI_BASE_ADDR 0x10000000 29#define MX2x_AIPI_BASE_ADDR 0x10000000
30#define AIPI_BASE_ADDR_VIRT 0xF4000000 30#define MX2x_AIPI_BASE_ADDR_VIRT 0xf4000000
31#define AIPI_SIZE SZ_1M 31#define MX2x_AIPI_SIZE SZ_1M
32 32#define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000)
33#define DMA_BASE_ADDR (AIPI_BASE_ADDR + 0x01000) 33#define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000)
34#define WDOG_BASE_ADDR (AIPI_BASE_ADDR + 0x02000) 34#define MX2x_GPT1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x03000)
35#define GPT1_BASE_ADDR (AIPI_BASE_ADDR + 0x03000) 35#define MX2x_GPT2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x04000)
36#define GPT2_BASE_ADDR (AIPI_BASE_ADDR + 0x04000) 36#define MX2x_GPT3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x05000)
37#define GPT3_BASE_ADDR (AIPI_BASE_ADDR + 0x05000) 37#define MX2x_PWM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x06000)
38#define PWM_BASE_ADDR (AIPI_BASE_ADDR + 0x06000) 38#define MX2x_RTC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x07000)
39#define RTC_BASE_ADDR (AIPI_BASE_ADDR + 0x07000) 39#define MX2x_KPP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x08000)
40#define KPP_BASE_ADDR (AIPI_BASE_ADDR + 0x08000) 40#define MX2x_OWIRE_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x09000)
41#define OWIRE_BASE_ADDR (AIPI_BASE_ADDR + 0x09000) 41#define MX2x_UART1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0a000)
42#define UART1_BASE_ADDR (AIPI_BASE_ADDR + 0x0A000) 42#define MX2x_UART2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0b000)
43#define UART2_BASE_ADDR (AIPI_BASE_ADDR + 0x0B000) 43#define MX2x_UART3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0c000)
44#define UART3_BASE_ADDR (AIPI_BASE_ADDR + 0x0C000) 44#define MX2x_UART4_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0d000)
45#define UART4_BASE_ADDR (AIPI_BASE_ADDR + 0x0D000) 45#define MX2x_CSPI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0e000)
46#define CSPI1_BASE_ADDR (AIPI_BASE_ADDR + 0x0E000) 46#define MX2x_CSPI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0f000)
47#define CSPI2_BASE_ADDR (AIPI_BASE_ADDR + 0x0F000) 47#define MX2x_SSI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x10000)
48#define SSI1_BASE_ADDR (AIPI_BASE_ADDR + 0x10000) 48#define MX2x_SSI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x11000)
49#define SSI2_BASE_ADDR (AIPI_BASE_ADDR + 0x11000) 49#define MX2x_I2C_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x12000)
50#define I2C_BASE_ADDR (AIPI_BASE_ADDR + 0x12000) 50#define MX2x_SDHC1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x13000)
51#define SDHC1_BASE_ADDR (AIPI_BASE_ADDR + 0x13000) 51#define MX2x_SDHC2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x14000)
52#define SDHC2_BASE_ADDR (AIPI_BASE_ADDR + 0x14000) 52#define MX2x_GPIO_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x15000)
53#define GPIO_BASE_ADDR (AIPI_BASE_ADDR + 0x15000) 53#define MX2x_AUDMUX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x16000)
54#define AUDMUX_BASE_ADDR (AIPI_BASE_ADDR + 0x16000) 54#define MX2x_CSPI3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x17000)
55#define CSPI3_BASE_ADDR (AIPI_BASE_ADDR + 0x17000) 55#define MX2x_LCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x21000)
56#define LCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x21000) 56#define MX2x_SLCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x22000)
57#define SLCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x22000) 57#define MX2x_USBOTG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x24000)
58#define USBOTG_BASE_ADDR (AIPI_BASE_ADDR + 0x24000) 58#define MX2x_EMMA_PP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26000)
59#define EMMA_PP_BASE_ADDR (AIPI_BASE_ADDR + 0x26000) 59#define MX2x_EMMA_PRP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26400)
60#define EMMA_PRP_BASE_ADDR (AIPI_BASE_ADDR + 0x26400) 60#define MX2x_CCM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27000)
61#define CCM_BASE_ADDR (AIPI_BASE_ADDR + 0x27000) 61#define MX2x_SYSCTRL_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27800)
62#define SYSCTRL_BASE_ADDR (AIPI_BASE_ADDR + 0x27800) 62#define MX2x_JAM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3e000)
63#define JAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3E000) 63#define MX2x_MAX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3f000)
64#define MAX_BASE_ADDR (AIPI_BASE_ADDR + 0x3F000) 64
65 65#define MX2x_AVIC_BASE_ADDR 0x10040000
66#define AVIC_BASE_ADDR 0x10040000 66
67 67#define MX2x_SAHB1_BASE_ADDR 0x80000000
68#define SAHB1_BASE_ADDR 0x80000000 68#define MX2x_SAHB1_BASE_ADDR_VIRT 0xf4100000
69#define SAHB1_BASE_ADDR_VIRT 0xF4100000 69#define MX2x_SAHB1_SIZE SZ_1M
70#define SAHB1_SIZE SZ_1M 70#define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
71
72#define CSI_BASE_ADDR (SAHB1_BASE_ADDR + 0x0000)
73 71
74/* 72/*
75 * This macro defines the physical to virtual address mapping for all the 73 * This macro defines the physical to virtual address mapping for all the
@@ -105,78 +103,189 @@
105 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) 103 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
106 104
107/* fixed interrupt numbers */ 105/* fixed interrupt numbers */
108#define MXC_INT_CSPI3 6 106#define MX2x_INT_CSPI3 6
109#define MXC_INT_GPIO 8 107#define MX2x_INT_GPIO 8
110#define MXC_INT_SDHC2 10 108#define MX2x_INT_SDHC2 10
111#define MXC_INT_SDHC1 11 109#define MX2x_INT_SDHC1 11
112#define MXC_INT_I2C 12 110#define MX2x_INT_I2C 12
113#define MXC_INT_SSI2 13 111#define MX2x_INT_SSI2 13
114#define MXC_INT_SSI1 14 112#define MX2x_INT_SSI1 14
115#define MXC_INT_CSPI2 15 113#define MX2x_INT_CSPI2 15
116#define MXC_INT_CSPI1 16 114#define MX2x_INT_CSPI1 16
117#define MXC_INT_UART4 17 115#define MX2x_INT_UART4 17
118#define MXC_INT_UART3 18 116#define MX2x_INT_UART3 18
119#define MXC_INT_UART2 19 117#define MX2x_INT_UART2 19
120#define MXC_INT_UART1 20 118#define MX2x_INT_UART1 20
121#define MXC_INT_KPP 21 119#define MX2x_INT_KPP 21
122#define MXC_INT_RTC 22 120#define MX2x_INT_RTC 22
123#define MXC_INT_PWM 23 121#define MX2x_INT_PWM 23
124#define MXC_INT_GPT INT_GPT1 122#define MX2x_INT_GPT3 24
125#define MXC_INT_GPT3 24 123#define MX2x_INT_GPT2 25
126#define MXC_INT_GPT2 25 124#define MX2x_INT_GPT1 26
127#define MXC_INT_GPT1 26 125#define MX2x_INT_WDOG 27
128#define MXC_INT_WDOG 27 126#define MX2x_INT_PCMCIA 28
129#define MXC_INT_PCMCIA 28 127#define MX2x_INT_NANDFC 29
130#define MXC_INT_NANDFC 29 128#define MX2x_INT_CSI 31
131#define MXC_INT_CSI 31 129#define MX2x_INT_DMACH0 32
132#define MXC_INT_DMACH0 32 130#define MX2x_INT_DMACH1 33
133#define MXC_INT_DMACH1 33 131#define MX2x_INT_DMACH2 34
134#define MXC_INT_DMACH2 34 132#define MX2x_INT_DMACH3 35
135#define MXC_INT_DMACH3 35 133#define MX2x_INT_DMACH4 36
136#define MXC_INT_DMACH4 36 134#define MX2x_INT_DMACH5 37
137#define MXC_INT_DMACH5 37 135#define MX2x_INT_DMACH6 38
138#define MXC_INT_DMACH6 38 136#define MX2x_INT_DMACH7 39
139#define MXC_INT_DMACH7 39 137#define MX2x_INT_DMACH8 40
140#define MXC_INT_DMACH8 40 138#define MX2x_INT_DMACH9 41
141#define MXC_INT_DMACH9 41 139#define MX2x_INT_DMACH10 42
142#define MXC_INT_DMACH10 42 140#define MX2x_INT_DMACH11 43
143#define MXC_INT_DMACH11 43 141#define MX2x_INT_DMACH12 44
144#define MXC_INT_DMACH12 44 142#define MX2x_INT_DMACH13 45
145#define MXC_INT_DMACH13 45 143#define MX2x_INT_DMACH14 46
146#define MXC_INT_DMACH14 46 144#define MX2x_INT_DMACH15 47
147#define MXC_INT_DMACH15 47 145#define MX2x_INT_EMMAPRP 51
148#define MXC_INT_EMMAPRP 51 146#define MX2x_INT_EMMAPP 52
149#define MXC_INT_EMMAPP 52 147#define MX2x_INT_SLCDC 60
150#define MXC_INT_SLCDC 60 148#define MX2x_INT_LCDC 61
151#define MXC_INT_LCDC 61
152 149
153/* fixed DMA request numbers */ 150/* fixed DMA request numbers */
154#define DMA_REQ_CSPI3_RX 1 151#define MX2x_DMA_REQ_CSPI3_RX 1
155#define DMA_REQ_CSPI3_TX 2 152#define MX2x_DMA_REQ_CSPI3_TX 2
156#define DMA_REQ_EXT 3 153#define MX2x_DMA_REQ_EXT 3
157#define DMA_REQ_SDHC2 6 154#define MX2x_DMA_REQ_SDHC2 6
158#define DMA_REQ_SDHC1 7 155#define MX2x_DMA_REQ_SDHC1 7
159#define DMA_REQ_SSI2_RX0 8 156#define MX2x_DMA_REQ_SSI2_RX0 8
160#define DMA_REQ_SSI2_TX0 9 157#define MX2x_DMA_REQ_SSI2_TX0 9
161#define DMA_REQ_SSI2_RX1 10 158#define MX2x_DMA_REQ_SSI2_RX1 10
162#define DMA_REQ_SSI2_TX1 11 159#define MX2x_DMA_REQ_SSI2_TX1 11
163#define DMA_REQ_SSI1_RX0 12 160#define MX2x_DMA_REQ_SSI1_RX0 12
164#define DMA_REQ_SSI1_TX0 13 161#define MX2x_DMA_REQ_SSI1_TX0 13
165#define DMA_REQ_SSI1_RX1 14 162#define MX2x_DMA_REQ_SSI1_RX1 14
166#define DMA_REQ_SSI1_TX1 15 163#define MX2x_DMA_REQ_SSI1_TX1 15
167#define DMA_REQ_CSPI2_RX 16 164#define MX2x_DMA_REQ_CSPI2_RX 16
168#define DMA_REQ_CSPI2_TX 17 165#define MX2x_DMA_REQ_CSPI2_TX 17
169#define DMA_REQ_CSPI1_RX 18 166#define MX2x_DMA_REQ_CSPI1_RX 18
170#define DMA_REQ_CSPI1_TX 19 167#define MX2x_DMA_REQ_CSPI1_TX 19
171#define DMA_REQ_UART4_RX 20 168#define MX2x_DMA_REQ_UART4_RX 20
172#define DMA_REQ_UART4_TX 21 169#define MX2x_DMA_REQ_UART4_TX 21
173#define DMA_REQ_UART3_RX 22 170#define MX2x_DMA_REQ_UART3_RX 22
174#define DMA_REQ_UART3_TX 23 171#define MX2x_DMA_REQ_UART3_TX 23
175#define DMA_REQ_UART2_RX 24 172#define MX2x_DMA_REQ_UART2_RX 24
176#define DMA_REQ_UART2_TX 25 173#define MX2x_DMA_REQ_UART2_TX 25
177#define DMA_REQ_UART1_RX 26 174#define MX2x_DMA_REQ_UART1_RX 26
178#define DMA_REQ_UART1_TX 27 175#define MX2x_DMA_REQ_UART1_TX 27
179#define DMA_REQ_CSI_STAT 30 176#define MX2x_DMA_REQ_CSI_STAT 30
180#define DMA_REQ_CSI_RX 31 177#define MX2x_DMA_REQ_CSI_RX 31
178
179/* these should go away */
180#define AIPI_BASE_ADDR MX2x_AIPI_BASE_ADDR
181#define AIPI_BASE_ADDR_VIRT MX2x_AIPI_BASE_ADDR_VIRT
182#define AIPI_SIZE MX2x_AIPI_SIZE
183#define DMA_BASE_ADDR MX2x_DMA_BASE_ADDR
184#define WDOG_BASE_ADDR MX2x_WDOG_BASE_ADDR
185#define GPT1_BASE_ADDR MX2x_GPT1_BASE_ADDR
186#define GPT2_BASE_ADDR MX2x_GPT2_BASE_ADDR
187#define GPT3_BASE_ADDR MX2x_GPT3_BASE_ADDR
188#define PWM_BASE_ADDR MX2x_PWM_BASE_ADDR
189#define RTC_BASE_ADDR MX2x_RTC_BASE_ADDR
190#define KPP_BASE_ADDR MX2x_KPP_BASE_ADDR
191#define OWIRE_BASE_ADDR MX2x_OWIRE_BASE_ADDR
192#define UART1_BASE_ADDR MX2x_UART1_BASE_ADDR
193#define UART2_BASE_ADDR MX2x_UART2_BASE_ADDR
194#define UART3_BASE_ADDR MX2x_UART3_BASE_ADDR
195#define UART4_BASE_ADDR MX2x_UART4_BASE_ADDR
196#define CSPI1_BASE_ADDR MX2x_CSPI1_BASE_ADDR
197#define CSPI2_BASE_ADDR MX2x_CSPI2_BASE_ADDR
198#define SSI1_BASE_ADDR MX2x_SSI1_BASE_ADDR
199#define SSI2_BASE_ADDR MX2x_SSI2_BASE_ADDR
200#define I2C_BASE_ADDR MX2x_I2C_BASE_ADDR
201#define SDHC1_BASE_ADDR MX2x_SDHC1_BASE_ADDR
202#define SDHC2_BASE_ADDR MX2x_SDHC2_BASE_ADDR
203#define GPIO_BASE_ADDR MX2x_GPIO_BASE_ADDR
204#define AUDMUX_BASE_ADDR MX2x_AUDMUX_BASE_ADDR
205#define CSPI3_BASE_ADDR MX2x_CSPI3_BASE_ADDR
206#define LCDC_BASE_ADDR MX2x_LCDC_BASE_ADDR
207#define SLCDC_BASE_ADDR MX2x_SLCDC_BASE_ADDR
208#define USBOTG_BASE_ADDR MX2x_USBOTG_BASE_ADDR
209#define EMMA_PP_BASE_ADDR MX2x_EMMA_PP_BASE_ADDR
210#define EMMA_PRP_BASE_ADDR MX2x_EMMA_PRP_BASE_ADDR
211#define CCM_BASE_ADDR MX2x_CCM_BASE_ADDR
212#define SYSCTRL_BASE_ADDR MX2x_SYSCTRL_BASE_ADDR
213#define JAM_BASE_ADDR MX2x_JAM_BASE_ADDR
214#define MAX_BASE_ADDR MX2x_MAX_BASE_ADDR
215#define AVIC_BASE_ADDR MX2x_AVIC_BASE_ADDR
216#define SAHB1_BASE_ADDR MX2x_SAHB1_BASE_ADDR
217#define SAHB1_BASE_ADDR_VIRT MX2x_SAHB1_BASE_ADDR_VIRT
218#define SAHB1_SIZE MX2x_SAHB1_SIZE
219#define CSI_BASE_ADDR MX2x_CSI_BASE_ADDR
220#define MXC_INT_CSPI3 MX2x_INT_CSPI3
221#define MXC_INT_GPIO MX2x_INT_GPIO
222#define MXC_INT_SDHC2 MX2x_INT_SDHC2
223#define MXC_INT_SDHC1 MX2x_INT_SDHC1
224#define MXC_INT_I2C MX2x_INT_I2C
225#define MXC_INT_SSI2 MX2x_INT_SSI2
226#define MXC_INT_SSI1 MX2x_INT_SSI1
227#define MXC_INT_CSPI2 MX2x_INT_CSPI2
228#define MXC_INT_CSPI1 MX2x_INT_CSPI1
229#define MXC_INT_UART4 MX2x_INT_UART4
230#define MXC_INT_UART3 MX2x_INT_UART3
231#define MXC_INT_UART2 MX2x_INT_UART2
232#define MXC_INT_UART1 MX2x_INT_UART1
233#define MXC_INT_KPP MX2x_INT_KPP
234#define MXC_INT_RTC MX2x_INT_RTC
235#define MXC_INT_PWM MX2x_INT_PWM
236#define MXC_INT_GPT3 MX2x_INT_GPT3
237#define MXC_INT_GPT2 MX2x_INT_GPT2
238#define MXC_INT_GPT1 MX2x_INT_GPT1
239#define MXC_INT_WDOG MX2x_INT_WDOG
240#define MXC_INT_PCMCIA MX2x_INT_PCMCIA
241#define MXC_INT_NANDFC MX2x_INT_NANDFC
242#define MXC_INT_CSI MX2x_INT_CSI
243#define MXC_INT_DMACH0 MX2x_INT_DMACH0
244#define MXC_INT_DMACH1 MX2x_INT_DMACH1
245#define MXC_INT_DMACH2 MX2x_INT_DMACH2
246#define MXC_INT_DMACH3 MX2x_INT_DMACH3
247#define MXC_INT_DMACH4 MX2x_INT_DMACH4
248#define MXC_INT_DMACH5 MX2x_INT_DMACH5
249#define MXC_INT_DMACH6 MX2x_INT_DMACH6
250#define MXC_INT_DMACH7 MX2x_INT_DMACH7
251#define MXC_INT_DMACH8 MX2x_INT_DMACH8
252#define MXC_INT_DMACH9 MX2x_INT_DMACH9
253#define MXC_INT_DMACH10 MX2x_INT_DMACH10
254#define MXC_INT_DMACH11 MX2x_INT_DMACH11
255#define MXC_INT_DMACH12 MX2x_INT_DMACH12
256#define MXC_INT_DMACH13 MX2x_INT_DMACH13
257#define MXC_INT_DMACH14 MX2x_INT_DMACH14
258#define MXC_INT_DMACH15 MX2x_INT_DMACH15
259#define MXC_INT_EMMAPRP MX2x_INT_EMMAPRP
260#define MXC_INT_EMMAPP MX2x_INT_EMMAPP
261#define MXC_INT_SLCDC MX2x_INT_SLCDC
262#define MXC_INT_LCDC MX2x_INT_LCDC
263#define DMA_REQ_CSPI3_RX MX2x_DMA_REQ_CSPI3_RX
264#define DMA_REQ_CSPI3_TX MX2x_DMA_REQ_CSPI3_TX
265#define DMA_REQ_EXT MX2x_DMA_REQ_EXT
266#define DMA_REQ_SDHC2 MX2x_DMA_REQ_SDHC2
267#define DMA_REQ_SDHC1 MX2x_DMA_REQ_SDHC1
268#define DMA_REQ_SSI2_RX0 MX2x_DMA_REQ_SSI2_RX0
269#define DMA_REQ_SSI2_TX0 MX2x_DMA_REQ_SSI2_TX0
270#define DMA_REQ_SSI2_RX1 MX2x_DMA_REQ_SSI2_RX1
271#define DMA_REQ_SSI2_TX1 MX2x_DMA_REQ_SSI2_TX1
272#define DMA_REQ_SSI1_RX0 MX2x_DMA_REQ_SSI1_RX0
273#define DMA_REQ_SSI1_TX0 MX2x_DMA_REQ_SSI1_TX0
274#define DMA_REQ_SSI1_RX1 MX2x_DMA_REQ_SSI1_RX1
275#define DMA_REQ_SSI1_TX1 MX2x_DMA_REQ_SSI1_TX1
276#define DMA_REQ_CSPI2_RX MX2x_DMA_REQ_CSPI2_RX
277#define DMA_REQ_CSPI2_TX MX2x_DMA_REQ_CSPI2_TX
278#define DMA_REQ_CSPI1_RX MX2x_DMA_REQ_CSPI1_RX
279#define DMA_REQ_CSPI1_TX MX2x_DMA_REQ_CSPI1_TX
280#define DMA_REQ_UART4_RX MX2x_DMA_REQ_UART4_RX
281#define DMA_REQ_UART4_TX MX2x_DMA_REQ_UART4_TX
282#define DMA_REQ_UART3_RX MX2x_DMA_REQ_UART3_RX
283#define DMA_REQ_UART3_TX MX2x_DMA_REQ_UART3_TX
284#define DMA_REQ_UART2_RX MX2x_DMA_REQ_UART2_RX
285#define DMA_REQ_UART2_TX MX2x_DMA_REQ_UART2_TX
286#define DMA_REQ_UART1_RX MX2x_DMA_REQ_UART1_RX
287#define DMA_REQ_UART1_TX MX2x_DMA_REQ_UART1_TX
288#define DMA_REQ_CSI_STAT MX2x_DMA_REQ_CSI_STAT
289#define DMA_REQ_CSI_RX MX2x_DMA_REQ_CSI_RX
181 290
182#endif /* __ASM_ARCH_MXC_MX2x_H__ */ 291#endif /* __ASM_ARCH_MXC_MX2x_H__ */