diff options
author | Sascha Hauer <s.hauer@pengutronix.de> | 2009-04-17 10:52:25 -0400 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2009-08-14 06:41:01 -0400 |
commit | 7bc07ebc7d2e9ad57baf205840ce31e9243ed5e8 (patch) | |
tree | 051fe744b671a3a717e4b7059fa9eabde3b56a6a /arch/arm/plat-mxc | |
parent | 337316986f0531e1681c409de9b73af0bc6dc7bb (diff) |
mx3x: Fixup USB base addresses
The i.MX31 and the i.MX35 have different USB base addresses. Adjust
the resources accordingly.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/plat-mxc')
-rw-r--r-- | arch/arm/plat-mxc/include/mach/mx31.h | 2 | ||||
-rw-r--r-- | arch/arm/plat-mxc/include/mach/mx35.h | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index 0b06941b6139..14ac0dcc82f4 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h | |||
@@ -4,7 +4,7 @@ | |||
4 | #define MX31_IRAM_BASE_ADDR 0x1FFC0000 /* internal ram */ | 4 | #define MX31_IRAM_BASE_ADDR 0x1FFC0000 /* internal ram */ |
5 | #define MX31_IRAM_SIZE SZ_16K | 5 | #define MX31_IRAM_SIZE SZ_16K |
6 | 6 | ||
7 | #define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) | 7 | #define MX31_OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) |
8 | #define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) | 8 | #define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) |
9 | #define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) | 9 | #define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) |
10 | #define UART5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) | 10 | #define UART5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) |
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h index 6465fefb42e3..ab4cfec6c8ab 100644 --- a/arch/arm/plat-mxc/include/mach/mx35.h +++ b/arch/arm/plat-mxc/include/mach/mx35.h | |||
@@ -5,6 +5,7 @@ | |||
5 | #define MX35_IRAM_SIZE SZ_128K | 5 | #define MX35_IRAM_SIZE SZ_128K |
6 | 6 | ||
7 | #define MXC_FEC_BASE_ADDR 0x50038000 | 7 | #define MXC_FEC_BASE_ADDR 0x50038000 |
8 | #define MX35_OTG_BASE_ADDR 0x53ff4000 | ||
8 | #define MX35_NFC_BASE_ADDR 0xBB000000 | 9 | #define MX35_NFC_BASE_ADDR 0xBB000000 |
9 | 10 | ||
10 | /* | 11 | /* |