diff options
author | Uwe Kleine-König <u.kleine-koenig@pengutronix.de> | 2011-07-25 06:05:09 -0400 |
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committer | Uwe Kleine-König <u.kleine-koenig@pengutronix.de> | 2011-08-01 05:16:54 -0400 |
commit | 1a1952779b8e92a404dceaecca70ba120bea2d94 (patch) | |
tree | cb0da287c428240c6f2ed3018d96a04b0d3d7916 /arch/arm/plat-mxc | |
parent | 3da3f872aa175f59e20766ed30aaea67fd4fa7d1 (diff) |
ARM: mx5: fix remaining inconsistent names for irqs
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Diffstat (limited to 'arch/arm/plat-mxc')
-rw-r--r-- | arch/arm/plat-mxc/include/mach/mx51.h | 162 |
1 files changed, 81 insertions, 81 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index dede19a766ff..d240b6f267b1 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h | |||
@@ -240,110 +240,110 @@ | |||
240 | /* | 240 | /* |
241 | * Interrupt numbers | 241 | * Interrupt numbers |
242 | */ | 242 | */ |
243 | #define MX51_MXC_INT_BASE 0 | 243 | #define MX51_INT_BASE 0 |
244 | #define MX51_MXC_INT_RESV0 0 | 244 | #define MX51_INT_RESV0 0 |
245 | #define MX51_INT_ESDHC1 1 | 245 | #define MX51_INT_ESDHC1 1 |
246 | #define MX51_INT_ESDHC2 2 | 246 | #define MX51_INT_ESDHC2 2 |
247 | #define MX51_INT_ESDHC3 3 | 247 | #define MX51_INT_ESDHC3 3 |
248 | #define MX51_INT_ESDHC4 4 | 248 | #define MX51_INT_ESDHC4 4 |
249 | #define MX51_MXC_INT_RESV5 5 | 249 | #define MX51_INT_RESV5 5 |
250 | #define MX51_INT_SDMA 6 | 250 | #define MX51_INT_SDMA 6 |
251 | #define MX51_MXC_INT_IOMUX 7 | 251 | #define MX51_INT_IOMUX 7 |
252 | #define MX51_INT_NFC 8 | 252 | #define MX51_INT_NFC 8 |
253 | #define MX51_MXC_INT_VPU 9 | 253 | #define MX51_INT_VPU 9 |
254 | #define MX51_INT_IPU_ERR 10 | 254 | #define MX51_INT_IPU_ERR 10 |
255 | #define MX51_INT_IPU_SYN 11 | 255 | #define MX51_INT_IPU_SYN 11 |
256 | #define MX51_MXC_INT_GPU 12 | 256 | #define MX51_INT_GPU 12 |
257 | #define MX51_MXC_INT_RESV13 13 | 257 | #define MX51_INT_RESV13 13 |
258 | #define MX51_MXC_INT_USB_H1 14 | 258 | #define MX51_INT_USB_H1 14 |
259 | #define MX51_MXC_INT_EMI 15 | 259 | #define MX51_INT_EMI 15 |
260 | #define MX51_MXC_INT_USB_H2 16 | 260 | #define MX51_INT_USB_H2 16 |
261 | #define MX51_MXC_INT_USB_H3 17 | 261 | #define MX51_INT_USB_H3 17 |
262 | #define MX51_MXC_INT_USB_OTG 18 | 262 | #define MX51_INT_USB_OTG 18 |
263 | #define MX51_MXC_INT_SAHARA_H0 19 | 263 | #define MX51_INT_SAHARA_H0 19 |
264 | #define MX51_MXC_INT_SAHARA_H1 20 | 264 | #define MX51_INT_SAHARA_H1 20 |
265 | #define MX51_MXC_INT_SCC_SMN 21 | 265 | #define MX51_INT_SCC_SMN 21 |
266 | #define MX51_MXC_INT_SCC_STZ 22 | 266 | #define MX51_INT_SCC_STZ 22 |
267 | #define MX51_MXC_INT_SCC_SCM 23 | 267 | #define MX51_INT_SCC_SCM 23 |
268 | #define MX51_MXC_INT_SRTC_NTZ 24 | 268 | #define MX51_INT_SRTC_NTZ 24 |
269 | #define MX51_MXC_INT_SRTC_TZ 25 | 269 | #define MX51_INT_SRTC_TZ 25 |
270 | #define MX51_MXC_INT_RTIC 26 | 270 | #define MX51_INT_RTIC 26 |
271 | #define MX51_MXC_INT_CSU 27 | 271 | #define MX51_INT_CSU 27 |
272 | #define MX51_MXC_INT_SLIM_B 28 | 272 | #define MX51_INT_SLIM_B 28 |
273 | #define MX51_INT_SSI1 29 | 273 | #define MX51_INT_SSI1 29 |
274 | #define MX51_INT_SSI2 30 | 274 | #define MX51_INT_SSI2 30 |
275 | #define MX51_INT_UART1 31 | 275 | #define MX51_INT_UART1 31 |
276 | #define MX51_INT_UART2 32 | 276 | #define MX51_INT_UART2 32 |
277 | #define MX51_INT_UART3 33 | 277 | #define MX51_INT_UART3 33 |
278 | #define MX51_MXC_INT_RESV34 34 | 278 | #define MX51_INT_RESV34 34 |
279 | #define MX51_MXC_INT_RESV35 35 | 279 | #define MX51_INT_RESV35 35 |
280 | #define MX51_INT_ECSPI1 36 | 280 | #define MX51_INT_ECSPI1 36 |
281 | #define MX51_INT_ECSPI2 37 | 281 | #define MX51_INT_ECSPI2 37 |
282 | #define MX51_INT_CSPI 38 | 282 | #define MX51_INT_CSPI 38 |
283 | #define MX51_MXC_INT_GPT 39 | 283 | #define MX51_INT_GPT 39 |
284 | #define MX51_MXC_INT_EPIT1 40 | 284 | #define MX51_INT_EPIT1 40 |
285 | #define MX51_MXC_INT_EPIT2 41 | 285 | #define MX51_INT_EPIT2 41 |
286 | #define MX51_MXC_INT_GPIO1_INT7 42 | 286 | #define MX51_INT_GPIO1_INT7 42 |
287 | #define MX51_MXC_INT_GPIO1_INT6 43 | 287 | #define MX51_INT_GPIO1_INT6 43 |
288 | #define MX51_MXC_INT_GPIO1_INT5 44 | 288 | #define MX51_INT_GPIO1_INT5 44 |
289 | #define MX51_MXC_INT_GPIO1_INT4 45 | 289 | #define MX51_INT_GPIO1_INT4 45 |
290 | #define MX51_MXC_INT_GPIO1_INT3 46 | 290 | #define MX51_INT_GPIO1_INT3 46 |
291 | #define MX51_MXC_INT_GPIO1_INT2 47 | 291 | #define MX51_INT_GPIO1_INT2 47 |
292 | #define MX51_MXC_INT_GPIO1_INT1 48 | 292 | #define MX51_INT_GPIO1_INT1 48 |
293 | #define MX51_MXC_INT_GPIO1_INT0 49 | 293 | #define MX51_INT_GPIO1_INT0 49 |
294 | #define MX51_MXC_INT_GPIO1_LOW 50 | 294 | #define MX51_INT_GPIO1_LOW 50 |
295 | #define MX51_MXC_INT_GPIO1_HIGH 51 | 295 | #define MX51_INT_GPIO1_HIGH 51 |
296 | #define MX51_MXC_INT_GPIO2_LOW 52 | 296 | #define MX51_INT_GPIO2_LOW 52 |
297 | #define MX51_MXC_INT_GPIO2_HIGH 53 | 297 | #define MX51_INT_GPIO2_HIGH 53 |
298 | #define MX51_MXC_INT_GPIO3_LOW 54 | 298 | #define MX51_INT_GPIO3_LOW 54 |
299 | #define MX51_MXC_INT_GPIO3_HIGH 55 | 299 | #define MX51_INT_GPIO3_HIGH 55 |
300 | #define MX51_MXC_INT_GPIO4_LOW 56 | 300 | #define MX51_INT_GPIO4_LOW 56 |
301 | #define MX51_MXC_INT_GPIO4_HIGH 57 | 301 | #define MX51_INT_GPIO4_HIGH 57 |
302 | #define MX51_MXC_INT_WDOG1 58 | 302 | #define MX51_INT_WDOG1 58 |
303 | #define MX51_MXC_INT_WDOG2 59 | 303 | #define MX51_INT_WDOG2 59 |
304 | #define MX51_INT_KPP 60 | 304 | #define MX51_INT_KPP 60 |
305 | #define MX51_INT_PWM1 61 | 305 | #define MX51_INT_PWM1 61 |
306 | #define MX51_INT_I2C1 62 | 306 | #define MX51_INT_I2C1 62 |
307 | #define MX51_INT_I2C2 63 | 307 | #define MX51_INT_I2C2 63 |
308 | #define MX51_MXC_INT_HS_I2C 64 | 308 | #define MX51_INT_HS_I2C 64 |
309 | #define MX51_MXC_INT_RESV65 65 | 309 | #define MX51_INT_RESV65 65 |
310 | #define MX51_MXC_INT_RESV66 66 | 310 | #define MX51_INT_RESV66 66 |
311 | #define MX51_MXC_INT_SIM_IPB 67 | 311 | #define MX51_INT_SIM_IPB 67 |
312 | #define MX51_MXC_INT_SIM_DAT 68 | 312 | #define MX51_INT_SIM_DAT 68 |
313 | #define MX51_MXC_INT_IIM 69 | 313 | #define MX51_INT_IIM 69 |
314 | #define MX51_MXC_INT_ATA 70 | 314 | #define MX51_INT_ATA 70 |
315 | #define MX51_MXC_INT_CCM1 71 | 315 | #define MX51_INT_CCM1 71 |
316 | #define MX51_MXC_INT_CCM2 72 | 316 | #define MX51_INT_CCM2 72 |
317 | #define MX51_MXC_INT_GPC1 73 | 317 | #define MX51_INT_GPC1 73 |
318 | #define MX51_MXC_INT_GPC2 74 | 318 | #define MX51_INT_GPC2 74 |
319 | #define MX51_MXC_INT_SRC 75 | 319 | #define MX51_INT_SRC 75 |
320 | #define MX51_MXC_INT_NM 76 | 320 | #define MX51_INT_NM 76 |
321 | #define MX51_MXC_INT_PMU 77 | 321 | #define MX51_INT_PMU 77 |
322 | #define MX51_MXC_INT_CTI_IRQ 78 | 322 | #define MX51_INT_CTI_IRQ 78 |
323 | #define MX51_MXC_INT_CTI1_TG0 79 | 323 | #define MX51_INT_CTI1_TG0 79 |
324 | #define MX51_MXC_INT_CTI1_TG1 80 | 324 | #define MX51_INT_CTI1_TG1 80 |
325 | #define MX51_MXC_INT_MCG_ERR 81 | 325 | #define MX51_INT_MCG_ERR 81 |
326 | #define MX51_MXC_INT_MCG_TMR 82 | 326 | #define MX51_INT_MCG_TMR 82 |
327 | #define MX51_MXC_INT_MCG_FUNC 83 | 327 | #define MX51_INT_MCG_FUNC 83 |
328 | #define MX51_MXC_INT_GPU2_IRQ 84 | 328 | #define MX51_INT_GPU2_IRQ 84 |
329 | #define MX51_MXC_INT_GPU2_BUSY 85 | 329 | #define MX51_INT_GPU2_BUSY 85 |
330 | #define MX51_MXC_INT_RESV86 86 | 330 | #define MX51_INT_RESV86 86 |
331 | #define MX51_INT_FEC 87 | 331 | #define MX51_INT_FEC 87 |
332 | #define MX51_MXC_INT_OWIRE 88 | 332 | #define MX51_INT_OWIRE 88 |
333 | #define MX51_MXC_INT_CTI1_TG2 89 | 333 | #define MX51_INT_CTI1_TG2 89 |
334 | #define MX51_MXC_INT_SJC 90 | 334 | #define MX51_INT_SJC 90 |
335 | #define MX51_MXC_INT_SPDIF 91 | 335 | #define MX51_INT_SPDIF 91 |
336 | #define MX51_MXC_INT_TVE 92 | 336 | #define MX51_INT_TVE 92 |
337 | #define MX51_MXC_INT_FIRI 93 | 337 | #define MX51_INT_FIRI 93 |
338 | #define MX51_INT_PWM2 94 | 338 | #define MX51_INT_PWM2 94 |
339 | #define MX51_MXC_INT_SLIM_EXP 95 | 339 | #define MX51_INT_SLIM_EXP 95 |
340 | #define MX51_INT_SSI3 96 | 340 | #define MX51_INT_SSI3 96 |
341 | #define MX51_MXC_INT_EMI_BOOT 97 | 341 | #define MX51_INT_EMI_BOOT 97 |
342 | #define MX51_MXC_INT_CTI1_TG3 98 | 342 | #define MX51_INT_CTI1_TG3 98 |
343 | #define MX51_MXC_INT_SMC_RX 99 | 343 | #define MX51_INT_SMC_RX 99 |
344 | #define MX51_MXC_INT_VPU_IDLE 100 | 344 | #define MX51_INT_VPU_IDLE 100 |
345 | #define MX51_MXC_INT_EMI_NFC 101 | 345 | #define MX51_INT_EMI_NFC 101 |
346 | #define MX51_MXC_INT_GPU_IDLE 102 | 346 | #define MX51_INT_GPU_IDLE 102 |
347 | 347 | ||
348 | #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) | 348 | #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) |
349 | extern int mx51_revision(void); | 349 | extern int mx51_revision(void); |