diff options
author | Sascha Hauer <s.hauer@pengutronix.de> | 2010-03-25 03:44:12 -0400 |
---|---|---|
committer | Sascha Hauer <s.hauer@pengutronix.de> | 2010-03-25 03:44:12 -0400 |
commit | 0491fcbb76339cecbe4b6b1e862fb0c166bacf2d (patch) | |
tree | bedf421a0ccabbef074460c36d8129eed43c0d7e /arch/arm/plat-mxc | |
parent | ae7a3f13ab59784d9d5041d8ecb08477a049e2c6 (diff) | |
parent | fc300206ad07e771ed003d35b1dc179eaf0c508f (diff) |
Merge branch 'mx51' into mxc-rc
Diffstat (limited to 'arch/arm/plat-mxc')
-rw-r--r-- | arch/arm/plat-mxc/include/mach/mx51.h | 33 | ||||
-rw-r--r-- | arch/arm/plat-mxc/include/mach/uncompress.h | 4 |
2 files changed, 16 insertions, 21 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index 771532b6b4a6..5aad344d5651 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h | |||
@@ -14,7 +14,7 @@ | |||
14 | * FB100000 70000000 1M SPBA 0 | 14 | * FB100000 70000000 1M SPBA 0 |
15 | * FB000000 73F00000 1M AIPS 1 | 15 | * FB000000 73F00000 1M AIPS 1 |
16 | * FB200000 83F00000 1M AIPS 2 | 16 | * FB200000 83F00000 1M AIPS 2 |
17 | * FA100000 8FFFC000 16K TZIC (interrupt controller) | 17 | * 8FFFC000 16K TZIC (interrupt controller) |
18 | * 90000000 256M CSD0 SDRAM/DDR | 18 | * 90000000 256M CSD0 SDRAM/DDR |
19 | * A0000000 256M CSD1 SDRAM/DDR | 19 | * A0000000 256M CSD1 SDRAM/DDR |
20 | * B0000000 128M CS0 Flash | 20 | * B0000000 128M CS0 Flash |
@@ -23,11 +23,17 @@ | |||
23 | * C8000000 64M CS3 Flash | 23 | * C8000000 64M CS3 Flash |
24 | * CC000000 32M CS4 SRAM | 24 | * CC000000 32M CS4 SRAM |
25 | * CE000000 32M CS5 SRAM | 25 | * CE000000 32M CS5 SRAM |
26 | * F9000000 CFFF0000 64K NFC (NAND Flash AXI) | 26 | * CFFF0000 64K NFC (NAND Flash AXI) |
27 | * | 27 | * |
28 | */ | 28 | */ |
29 | 29 | ||
30 | /* | 30 | /* |
31 | * IROM | ||
32 | */ | ||
33 | #define MX51_IROM_BASE_ADDR 0x0 | ||
34 | #define MX51_IROM_SIZE SZ_64K | ||
35 | |||
36 | /* | ||
31 | * IRAM | 37 | * IRAM |
32 | */ | 38 | */ |
33 | #define MX51_IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ | 39 | #define MX51_IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ |
@@ -40,7 +46,6 @@ | |||
40 | * NFC | 46 | * NFC |
41 | */ | 47 | */ |
42 | #define MX51_NFC_AXI_BASE_ADDR 0xCFFF0000 /* NAND flash AXI */ | 48 | #define MX51_NFC_AXI_BASE_ADDR 0xCFFF0000 /* NAND flash AXI */ |
43 | #define MX51_NFC_AXI_BASE_ADDR_VIRT 0xF9000000 | ||
44 | #define MX51_NFC_AXI_SIZE SZ_64K | 49 | #define MX51_NFC_AXI_SIZE SZ_64K |
45 | 50 | ||
46 | /* | 51 | /* |
@@ -49,9 +54,8 @@ | |||
49 | #define MX51_GPU_BASE_ADDR 0x20000000 | 54 | #define MX51_GPU_BASE_ADDR 0x20000000 |
50 | #define MX51_GPU2D_BASE_ADDR 0xD0000000 | 55 | #define MX51_GPU2D_BASE_ADDR 0xD0000000 |
51 | 56 | ||
52 | #define MX51_TZIC_BASE_ADDR 0x8FFFC000 | 57 | #define MX51_TZIC_BASE_ADDR_TO1 0x8FFFC000 |
53 | #define MX51_TZIC_BASE_ADDR_VIRT 0xFA100000 | 58 | #define MX51_TZIC_BASE_ADDR 0xE0000000 |
54 | #define MX51_TZIC_SIZE SZ_16K | ||
55 | 59 | ||
56 | #define MX51_DEBUG_BASE_ADDR 0x60000000 | 60 | #define MX51_DEBUG_BASE_ADDR 0x60000000 |
57 | #define MX51_DEBUG_BASE_ADDR_VIRT 0xFA200000 | 61 | #define MX51_DEBUG_BASE_ADDR_VIRT 0xFA200000 |
@@ -232,12 +236,10 @@ | |||
232 | #define MX51_IO_ADDRESS(x) \ | 236 | #define MX51_IO_ADDRESS(x) \ |
233 | (void __iomem *) \ | 237 | (void __iomem *) \ |
234 | (MX51_IS_MODULE(x, IRAM) ? MX51_IRAM_IO_ADDRESS(x) : \ | 238 | (MX51_IS_MODULE(x, IRAM) ? MX51_IRAM_IO_ADDRESS(x) : \ |
235 | MX51_IS_MODULE(x, TZIC) ? MX51_TZIC_IO_ADDRESS(x) : \ | ||
236 | MX51_IS_MODULE(x, DEBUG) ? MX51_DEBUG_IO_ADDRESS(x) : \ | 239 | MX51_IS_MODULE(x, DEBUG) ? MX51_DEBUG_IO_ADDRESS(x) : \ |
237 | MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) : \ | 240 | MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) : \ |
238 | MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) : \ | 241 | MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) : \ |
239 | MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) : \ | 242 | MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) : \ |
240 | MX51_IS_MODULE(x, NFC_AXI) ? MX51_NFC_AXI_IO_ADDRESS(x) : \ | ||
241 | 0xDEADBEEF) | 243 | 0xDEADBEEF) |
242 | 244 | ||
243 | /* | 245 | /* |
@@ -246,9 +248,6 @@ | |||
246 | #define MX51_IRAM_IO_ADDRESS(x) \ | 248 | #define MX51_IRAM_IO_ADDRESS(x) \ |
247 | (((x) - MX51_IRAM_BASE_ADDR) + MX51_IRAM_BASE_ADDR_VIRT) | 249 | (((x) - MX51_IRAM_BASE_ADDR) + MX51_IRAM_BASE_ADDR_VIRT) |
248 | 250 | ||
249 | #define MX51_TZIC_IO_ADDRESS(x) \ | ||
250 | (((x) - MX51_TZIC_BASE_ADDR) + MX51_TZIC_BASE_ADDR_VIRT) | ||
251 | |||
252 | #define MX51_DEBUG_IO_ADDRESS(x) \ | 251 | #define MX51_DEBUG_IO_ADDRESS(x) \ |
253 | (((x) - MX51_DEBUG_BASE_ADDR) + MX51_DEBUG_BASE_ADDR_VIRT) | 252 | (((x) - MX51_DEBUG_BASE_ADDR) + MX51_DEBUG_BASE_ADDR_VIRT) |
254 | 253 | ||
@@ -261,9 +260,6 @@ | |||
261 | #define MX51_AIPS2_IO_ADDRESS(x) \ | 260 | #define MX51_AIPS2_IO_ADDRESS(x) \ |
262 | (((x) - MX51_AIPS2_BASE_ADDR) + MX51_AIPS2_BASE_ADDR_VIRT) | 261 | (((x) - MX51_AIPS2_BASE_ADDR) + MX51_AIPS2_BASE_ADDR_VIRT) |
263 | 262 | ||
264 | #define MX51_NFC_AXI_IO_ADDRESS(x) \ | ||
265 | (((x) - MX51_NFC_AXI_BASE_ADDR) + MX51_NFC_AXI_BASE_ADDR_VIRT) | ||
266 | |||
267 | #define MX51_IS_MEM_DEVICE_NONSHARED(x) 0 | 263 | #define MX51_IS_MEM_DEVICE_NONSHARED(x) 0 |
268 | 264 | ||
269 | /* | 265 | /* |
@@ -443,12 +439,7 @@ | |||
443 | 439 | ||
444 | #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) | 440 | #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) |
445 | 441 | ||
446 | extern unsigned int system_rev; | 442 | extern int mx51_revision(void); |
447 | |||
448 | static inline unsigned int mx51_revision(void) | ||
449 | { | ||
450 | return system_rev; | ||
451 | } | ||
452 | #endif | 443 | #endif |
453 | 444 | ||
454 | #endif /* __ASM_ARCH_MXC_MX51_H__ */ | 445 | #endif /* __ASM_ARCH_MXC_MX51_H__ */ |
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h index 52e476a150ca..b6d3d0fddc48 100644 --- a/arch/arm/plat-mxc/include/mach/uncompress.h +++ b/arch/arm/plat-mxc/include/mach/uncompress.h | |||
@@ -66,6 +66,7 @@ static inline void flush(void) | |||
66 | #define MX2X_UART1_BASE_ADDR 0x1000a000 | 66 | #define MX2X_UART1_BASE_ADDR 0x1000a000 |
67 | #define MX3X_UART1_BASE_ADDR 0x43F90000 | 67 | #define MX3X_UART1_BASE_ADDR 0x43F90000 |
68 | #define MX3X_UART2_BASE_ADDR 0x43F94000 | 68 | #define MX3X_UART2_BASE_ADDR 0x43F94000 |
69 | #define MX51_UART1_BASE_ADDR 0x73fbc000 | ||
69 | 70 | ||
70 | static __inline__ void __arch_decomp_setup(unsigned long arch_id) | 71 | static __inline__ void __arch_decomp_setup(unsigned long arch_id) |
71 | { | 72 | { |
@@ -101,6 +102,9 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id) | |||
101 | case MACH_TYPE_MAGX_ZN5: | 102 | case MACH_TYPE_MAGX_ZN5: |
102 | uart_base = MX3X_UART2_BASE_ADDR; | 103 | uart_base = MX3X_UART2_BASE_ADDR; |
103 | break; | 104 | break; |
105 | case MACH_TYPE_MX51_BABBAGE: | ||
106 | uart_base = MX51_UART1_BASE_ADDR; | ||
107 | break; | ||
104 | default: | 108 | default: |
105 | break; | 109 | break; |
106 | } | 110 | } |