diff options
author | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-01-06 17:33:32 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-01-06 17:33:32 -0500 |
commit | 404a02cbd2ae8bf256a2fa1169bdfe86bb5ebb34 (patch) | |
tree | 99119edc53fdca73ed7586829b8ee736e09440b3 /arch/arm/plat-mxc/tzic.c | |
parent | 28cdac6690cb113856293bf79b40de33dbd8f974 (diff) | |
parent | 1051b9f0f9eab8091fe3bf98320741adf36b4cfa (diff) |
Merge branch 'devel-stable' into devel
Conflicts:
arch/arm/mach-pxa/clock.c
arch/arm/mach-pxa/clock.h
Diffstat (limited to 'arch/arm/plat-mxc/tzic.c')
-rw-r--r-- | arch/arm/plat-mxc/tzic.c | 46 |
1 files changed, 39 insertions, 7 deletions
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c index 3703ab28257f..e69ed8a8c203 100644 --- a/arch/arm/plat-mxc/tzic.c +++ b/arch/arm/plat-mxc/tzic.c | |||
@@ -21,6 +21,8 @@ | |||
21 | #include <mach/hardware.h> | 21 | #include <mach/hardware.h> |
22 | #include <mach/common.h> | 22 | #include <mach/common.h> |
23 | 23 | ||
24 | #include "irq-common.h" | ||
25 | |||
24 | /* | 26 | /* |
25 | ***************************************** | 27 | ***************************************** |
26 | * TZIC Registers * | 28 | * TZIC Registers * |
@@ -47,6 +49,25 @@ | |||
47 | 49 | ||
48 | void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */ | 50 | void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */ |
49 | 51 | ||
52 | #ifdef CONFIG_FIQ | ||
53 | static int tzic_set_irq_fiq(unsigned int irq, unsigned int type) | ||
54 | { | ||
55 | unsigned int index, mask, value; | ||
56 | |||
57 | index = irq >> 5; | ||
58 | if (unlikely(index >= 4)) | ||
59 | return -EINVAL; | ||
60 | mask = 1U << (irq & 0x1F); | ||
61 | |||
62 | value = __raw_readl(tzic_base + TZIC_INTSEC0(index)) | mask; | ||
63 | if (type) | ||
64 | value &= ~mask; | ||
65 | __raw_writel(value, tzic_base + TZIC_INTSEC0(index)); | ||
66 | |||
67 | return 0; | ||
68 | } | ||
69 | #endif | ||
70 | |||
50 | /** | 71 | /** |
51 | * tzic_mask_irq() - Disable interrupt number "irq" in the TZIC | 72 | * tzic_mask_irq() - Disable interrupt number "irq" in the TZIC |
52 | * | 73 | * |
@@ -104,12 +125,17 @@ static int tzic_set_wake_irq(unsigned int irq, unsigned int enable) | |||
104 | return 0; | 125 | return 0; |
105 | } | 126 | } |
106 | 127 | ||
107 | static struct irq_chip mxc_tzic_chip = { | 128 | static struct mxc_irq_chip mxc_tzic_chip = { |
108 | .name = "MXC_TZIC", | 129 | .base = { |
109 | .ack = tzic_mask_irq, | 130 | .name = "MXC_TZIC", |
110 | .mask = tzic_mask_irq, | 131 | .ack = tzic_mask_irq, |
111 | .unmask = tzic_unmask_irq, | 132 | .mask = tzic_mask_irq, |
112 | .set_wake = tzic_set_wake_irq, | 133 | .unmask = tzic_unmask_irq, |
134 | .set_wake = tzic_set_wake_irq, | ||
135 | }, | ||
136 | #ifdef CONFIG_FIQ | ||
137 | .set_irq_fiq = tzic_set_irq_fiq, | ||
138 | #endif | ||
113 | }; | 139 | }; |
114 | 140 | ||
115 | /* | 141 | /* |
@@ -141,10 +167,16 @@ void __init tzic_init_irq(void __iomem *irqbase) | |||
141 | /* all IRQ no FIQ Warning :: No selection */ | 167 | /* all IRQ no FIQ Warning :: No selection */ |
142 | 168 | ||
143 | for (i = 0; i < MXC_INTERNAL_IRQS; i++) { | 169 | for (i = 0; i < MXC_INTERNAL_IRQS; i++) { |
144 | set_irq_chip(i, &mxc_tzic_chip); | 170 | set_irq_chip(i, &mxc_tzic_chip.base); |
145 | set_irq_handler(i, handle_level_irq); | 171 | set_irq_handler(i, handle_level_irq); |
146 | set_irq_flags(i, IRQF_VALID); | 172 | set_irq_flags(i, IRQF_VALID); |
147 | } | 173 | } |
174 | |||
175 | #ifdef CONFIG_FIQ | ||
176 | /* Initialize FIQ */ | ||
177 | init_FIQ(); | ||
178 | #endif | ||
179 | |||
148 | pr_info("TrustZone Interrupt Controller (TZIC) initialized\n"); | 180 | pr_info("TrustZone Interrupt Controller (TZIC) initialized\n"); |
149 | } | 181 | } |
150 | 182 | ||