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authorIngo Molnar <mingo@elte.hu>2009-09-19 05:27:32 -0400
committerIngo Molnar <mingo@elte.hu>2009-09-19 05:28:41 -0400
commit929bf0d0156562ce631728b6fa53d68004d456d2 (patch)
tree739063990a8077b29ef97e69d73bce94573daae4 /arch/arm/plat-mxc/system.c
parentdef0a9b2573e00ab0b486cb5382625203ab4c4a6 (diff)
parent202c4675c55ddf6b443c7e057d2dff6b42ef71aa (diff)
Merge branch 'linus' into perfcounters/core
Merge reason: Bring in tracing changes we depend on. Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/arm/plat-mxc/system.c')
-rw-r--r--arch/arm/plat-mxc/system.c29
1 files changed, 20 insertions, 9 deletions
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index 79c37577c916..97f42799fa58 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -27,32 +27,38 @@
27#include <linux/delay.h> 27#include <linux/delay.h>
28 28
29#include <mach/hardware.h> 29#include <mach/hardware.h>
30#include <mach/common.h>
30#include <asm/proc-fns.h> 31#include <asm/proc-fns.h>
31#include <asm/system.h> 32#include <asm/system.h>
32 33
33#ifdef CONFIG_ARCH_MX1 34static void __iomem *wdog_base;
34#define WDOG_WCR_REG IO_ADDRESS(WDT_BASE_ADDR)
35#define WDOG_WCR_ENABLE (1 << 0)
36#else
37#define WDOG_WCR_REG IO_ADDRESS(WDOG_BASE_ADDR)
38#define WDOG_WCR_ENABLE (1 << 2)
39#endif
40 35
41/* 36/*
42 * Reset the system. It is called by machine_restart(). 37 * Reset the system. It is called by machine_restart().
43 */ 38 */
44void arch_reset(char mode, const char *cmd) 39void arch_reset(char mode, const char *cmd)
45{ 40{
46 if (!cpu_is_mx1()) { 41 unsigned int wcr_enable;
42
43#ifdef CONFIG_ARCH_MXC91231
44 if (cpu_is_mxc91231()) {
45 mxc91231_arch_reset(mode, cmd);
46 return;
47 }
48#endif
49 if (cpu_is_mx1()) {
50 wcr_enable = (1 << 0);
51 } else {
47 struct clk *clk; 52 struct clk *clk;
48 53
49 clk = clk_get_sys("imx-wdt.0", NULL); 54 clk = clk_get_sys("imx-wdt.0", NULL);
50 if (!IS_ERR(clk)) 55 if (!IS_ERR(clk))
51 clk_enable(clk); 56 clk_enable(clk);
57 wcr_enable = (1 << 2);
52 } 58 }
53 59
54 /* Assert SRS signal */ 60 /* Assert SRS signal */
55 __raw_writew(WDOG_WCR_ENABLE, WDOG_WCR_REG); 61 __raw_writew(wcr_enable, wdog_base);
56 62
57 /* wait for reset to assert... */ 63 /* wait for reset to assert... */
58 mdelay(500); 64 mdelay(500);
@@ -65,3 +71,8 @@ void arch_reset(char mode, const char *cmd)
65 /* we'll take a jump through zero as a poor second */ 71 /* we'll take a jump through zero as a poor second */
66 cpu_reset(0); 72 cpu_reset(0);
67} 73}
74
75void mxc_arch_reset_init(void __iomem *base)
76{
77 wdog_base = base;
78}