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authorUwe Kleine-König <u.kleine-koenig@pengutronix.de>2010-06-30 06:16:24 -0400
committerUwe Kleine-König <u.kleine-koenig@pengutronix.de>2010-07-26 08:27:25 -0400
commit2dcf78c0eeae3bd07082821557014f25f02ca2e9 (patch)
tree8ca5c4c7f35c9a9ab07fcd9732124c905e609aa1 /arch/arm/plat-mxc/include
parent6b6322676add0fa2713d0ec89a28390fd4d907f5 (diff)
parent5109a4597f7e758b8d20694392d0361a0b4c43b1 (diff)
Merge branch 'imx/for-2.6.36' of git://git.pengutronix.de/git/ukl/linux-2.6 into HEAD
There are some more conflicts than detected by git, namely support for the newly added cpuimx machines needed to be converted to dynamic device registration. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Conflicts: arch/arm/mach-imx/Makefile arch/arm/mach-imx/devices.c arch/arm/mach-imx/devices.h arch/arm/mach-imx/eukrea_mbimx27-baseboard.c arch/arm/mach-mx2/Kconfig arch/arm/mach-mx25/Makefile arch/arm/mach-mx25/devices.c arch/arm/plat-mxc/include/mach/mx25.h arch/arm/plat-mxc/include/mach/mxc_nand.h
Diffstat (limited to 'arch/arm/plat-mxc/include')
-rw-r--r--arch/arm/plat-mxc/include/mach/board-armadillo5x0.h15
-rw-r--r--arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/board-kzmarm11.h39
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx21ads.h52
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx27ads.h344
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx27lite.h14
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx27pdk.h14
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31_3ds.h59
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31ads.h117
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31lilly.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31lite.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31moboard.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx35pdk.h22
-rw-r--r--arch/arm/plat-mxc/include/mach/board-pcm037.h22
-rw-r--r--arch/arm/plat-mxc/include/mach/board-pcm038.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/board-pcm043.h22
-rw-r--r--arch/arm/plat-mxc/include/mach/board-qong.h17
-rw-r--r--arch/arm/plat-mxc/include/mach/devices-common.h42
-rw-r--r--arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h105
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mxc91231.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/mx1.h28
-rw-r--r--arch/arm/plat-mxc/include/mach/mx25.h36
-rw-r--r--arch/arm/plat-mxc/include/mach/mx27.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/mx31.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/mx35.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/mx3_camera.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc91231.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc_nand.h6
-rw-r--r--arch/arm/plat-mxc/include/mach/system.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/timex.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/uncompress.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/vmalloc.h4
32 files changed, 98 insertions, 906 deletions
diff --git a/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h b/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h
deleted file mode 100644
index 0376c133c9f4..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/*
2 * Copyright 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>.
3 * All Rights Reserved.
4 */
5
6/*
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__
13#define __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__
14
15#endif
diff --git a/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h b/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h
index a1fd5830af48..45b2fb8bed61 100644
--- a/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h
+++ b/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h
@@ -25,7 +25,7 @@
25#ifndef __ASSEMBLY__ 25#ifndef __ASSEMBLY__
26/* 26/*
27 * This CPU module needs a baseboard to work. After basic initializing 27 * This CPU module needs a baseboard to work. After basic initializing
28 * its own devices, it calls baseboard's init function. 28 * its own devices, it calls the baseboard's init function.
29 * TODO: Add your own baseboard init function and call it from 29 * TODO: Add your own baseboard init function and call it from
30 * inside eukrea_cpuimx27_init(). 30 * inside eukrea_cpuimx27_init().
31 * 31 *
diff --git a/arch/arm/plat-mxc/include/mach/board-kzmarm11.h b/arch/arm/plat-mxc/include/mach/board-kzmarm11.h
deleted file mode 100644
index 93cc66f104c7..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-kzmarm11.h
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * Copyright (C) 2009 Yoichi Yuasa <yuasa@linux-mips.org>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18#ifndef __ARM_ARCH_BOARD_KZM_ARM11_H
19#define __ARM_ARCH_BOARD_KZM_ARM11_H
20
21/*
22 * KZM-ARM11-01 Board Control Registers on FPGA
23 */
24#define KZM_ARM11_CTL1 (MX31_CS4_BASE_ADDR + 0x1000)
25#define KZM_ARM11_CTL2 (MX31_CS4_BASE_ADDR + 0x1001)
26#define KZM_ARM11_RSW1 (MX31_CS4_BASE_ADDR + 0x1002)
27#define KZM_ARM11_BACK_LIGHT (MX31_CS4_BASE_ADDR + 0x1004)
28#define KZM_ARM11_FPGA_REV (MX31_CS4_BASE_ADDR + 0x1008)
29#define KZM_ARM11_7SEG_LED (MX31_CS4_BASE_ADDR + 0x1010)
30#define KZM_ARM11_LEDS (MX31_CS4_BASE_ADDR + 0x1020)
31#define KZM_ARM11_DIPSW2 (MX31_CS4_BASE_ADDR + 0x1003)
32
33/*
34 * External UART for touch panel on FPGA
35 */
36#define KZM_ARM11_16550 (MX31_CS4_BASE_ADDR + 0x1050)
37
38#endif /* __ARM_ARCH_BOARD_KZM_ARM11_H */
39
diff --git a/arch/arm/plat-mxc/include/mach/board-mx21ads.h b/arch/arm/plat-mxc/include/mach/board-mx21ads.h
deleted file mode 100644
index 0cf4fa29510c..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-mx21ads.h
+++ /dev/null
@@ -1,52 +0,0 @@
1/*
2 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14#ifndef __ASM_ARCH_MXC_BOARD_MX21ADS_H__
15#define __ASM_ARCH_MXC_BOARD_MX21ADS_H__
16
17/*
18 * Memory-mapped I/O on MX21ADS base board
19 */
20#define MX21ADS_MMIO_BASE_ADDR 0xF5000000
21#define MX21ADS_MMIO_SIZE SZ_16M
22
23#define MX21ADS_REG_ADDR(offset) (void __force __iomem *) \
24 (MX21ADS_MMIO_BASE_ADDR + (offset))
25
26#define MX21ADS_CS8900A_IRQ IRQ_GPIOE(11)
27#define MX21ADS_CS8900A_IOBASE_REG MX21ADS_REG_ADDR(0x000000)
28#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000)
29#define MX21ADS_VERSION_REG MX21ADS_REG_ADDR(0x400000)
30#define MX21ADS_IO_REG MX21ADS_REG_ADDR(0x800000)
31
32/* MX21ADS_IO_REG bit definitions */
33#define MX21ADS_IO_SD_WP 0x0001 /* read */
34#define MX21ADS_IO_TP6 0x0001 /* write */
35#define MX21ADS_IO_SW_SEL 0x0002 /* read */
36#define MX21ADS_IO_TP7 0x0002 /* write */
37#define MX21ADS_IO_RESET_E_UART 0x0004
38#define MX21ADS_IO_RESET_BASE 0x0008
39#define MX21ADS_IO_CSI_CTL2 0x0010
40#define MX21ADS_IO_CSI_CTL1 0x0020
41#define MX21ADS_IO_CSI_CTL0 0x0040
42#define MX21ADS_IO_UART1_EN 0x0080
43#define MX21ADS_IO_UART4_EN 0x0100
44#define MX21ADS_IO_LCDON 0x0200
45#define MX21ADS_IO_IRDA_EN 0x0400
46#define MX21ADS_IO_IRDA_FIR_SEL 0x0800
47#define MX21ADS_IO_IRDA_MD0_B 0x1000
48#define MX21ADS_IO_IRDA_MD1 0x2000
49#define MX21ADS_IO_LED4_ON 0x4000
50#define MX21ADS_IO_LED3_ON 0x8000
51
52#endif /* __ASM_ARCH_MXC_BOARD_MX21ADS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27ads.h b/arch/arm/plat-mxc/include/mach/board-mx27ads.h
deleted file mode 100644
index 7776d230327f..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-mx27ads.h
+++ /dev/null
@@ -1,344 +0,0 @@
1/*
2 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14#ifndef __ASM_ARCH_MXC_BOARD_MX27ADS_H__
15#define __ASM_ARCH_MXC_BOARD_MX27ADS_H__
16
17/* external interrupt multiplexer */
18#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
19
20#define MXC_VIRTUAL_INTS_BASE (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES)
21#define MXC_SDIO1_CARD_IRQ MXC_VIRTUAL_INTS_BASE
22#define MXC_SDIO2_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 1)
23#define MXC_SDIO3_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 2)
24
25#define MXC_MAX_BOARD_INTS (MXC_MAX_EXP_IO_LINES + \
26 MXC_MAX_VIRTUAL_INTS)
27
28/*
29 * @name Memory Size parameters
30 */
31
32/*
33 * Size of SDRAM memory
34 */
35#define SDRAM_MEM_SIZE SZ_128M
36
37/*
38 * PBC Controller parameters
39 */
40
41/*
42 * Base address of PBC controller, CS4
43 */
44#define PBC_BASE_ADDRESS 0xf4300000
45#define PBC_REG_ADDR(offset) (void __force __iomem *) \
46 (PBC_BASE_ADDRESS + (offset))
47
48/*
49 * PBC Interupt name definitions
50 */
51#define PBC_GPIO1_0 0
52#define PBC_GPIO1_1 1
53#define PBC_GPIO1_2 2
54#define PBC_GPIO1_3 3
55#define PBC_GPIO1_4 4
56#define PBC_GPIO1_5 5
57
58#define PBC_INTR_MAX_NUM 6
59#define PBC_INTR_SHARED_MAX_NUM 8
60
61/* When the PBC address connection is fixed in h/w, defined as 1 */
62#define PBC_ADDR_SH 0
63
64/* Offsets for the PBC Controller register */
65/*
66 * PBC Board version register offset
67 */
68#define PBC_VERSION_REG PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
69/*
70 * PBC Board control register 1 set address.
71 */
72#define PBC_BCTRL1_SET_REG PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
73/*
74 * PBC Board control register 1 clear address.
75 */
76#define PBC_BCTRL1_CLEAR_REG PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
77/*
78 * PBC Board control register 2 set address.
79 */
80#define PBC_BCTRL2_SET_REG PBC_REG_ADDR(0x00010 >> PBC_ADDR_SH)
81/*
82 * PBC Board control register 2 clear address.
83 */
84#define PBC_BCTRL2_CLEAR_REG PBC_REG_ADDR(0x00014 >> PBC_ADDR_SH)
85/*
86 * PBC Board control register 3 set address.
87 */
88#define PBC_BCTRL3_SET_REG PBC_REG_ADDR(0x00018 >> PBC_ADDR_SH)
89/*
90 * PBC Board control register 3 clear address.
91 */
92#define PBC_BCTRL3_CLEAR_REG PBC_REG_ADDR(0x0001C >> PBC_ADDR_SH)
93/*
94 * PBC Board control register 3 set address.
95 */
96#define PBC_BCTRL4_SET_REG PBC_REG_ADDR(0x00020 >> PBC_ADDR_SH)
97/*
98 * PBC Board control register 4 clear address.
99 */
100#define PBC_BCTRL4_CLEAR_REG PBC_REG_ADDR(0x00024 >> PBC_ADDR_SH)
101/*PBC_ADDR_SH
102 * PBC Board status register 1.
103 */
104#define PBC_BSTAT1_REG PBC_REG_ADDR(0x00028 >> PBC_ADDR_SH)
105/*
106 * PBC Board interrupt status register.
107 */
108#define PBC_INTSTATUS_REG PBC_REG_ADDR(0x0002C >> PBC_ADDR_SH)
109/*
110 * PBC Board interrupt current status register.
111 */
112#define PBC_INTCURR_STATUS_REG PBC_REG_ADDR(0x00034 >> PBC_ADDR_SH)
113/*
114 * PBC Interrupt mask register set address.
115 */
116#define PBC_INTMASK_SET_REG PBC_REG_ADDR(0x00038 >> PBC_ADDR_SH)
117/*
118 * PBC Interrupt mask register clear address.
119 */
120#define PBC_INTMASK_CLEAR_REG PBC_REG_ADDR(0x0003C >> PBC_ADDR_SH)
121/*
122 * External UART A.
123 */
124#define PBC_SC16C652_UARTA_REG PBC_REG_ADDR(0x20000 >> PBC_ADDR_SH)
125/*
126 * UART 4 Expanding Signal Status.
127 */
128#define PBC_UART_STATUS_REG PBC_REG_ADDR(0x22000 >> PBC_ADDR_SH)
129/*
130 * UART 4 Expanding Signal Control Set.
131 */
132#define PBC_UCTRL_SET_REG PBC_REG_ADDR(0x24000 >> PBC_ADDR_SH)
133/*
134 * UART 4 Expanding Signal Control Clear.
135 */
136#define PBC_UCTRL_CLR_REG PBC_REG_ADDR(0x26000 >> PBC_ADDR_SH)
137/*
138 * Ethernet Controller IO base address.
139 */
140#define PBC_CS8900A_IOBASE_REG PBC_REG_ADDR(0x40000 >> PBC_ADDR_SH)
141/*
142 * Ethernet Controller Memory base address.
143 */
144#define PBC_CS8900A_MEMBASE_REG PBC_REG_ADDR(0x42000 >> PBC_ADDR_SH)
145/*
146 * Ethernet Controller DMA base address.
147 */
148#define PBC_CS8900A_DMABASE_REG PBC_REG_ADDR(0x44000 >> PBC_ADDR_SH)
149
150/* PBC Board Version Register bit definition */
151#define PBC_VERSION_ADS 0x8000 /* Bit15=1 means version for ads */
152#define PBC_VERSION_EVB_REVB 0x4000 /* BIT14=1 means version for evb revb */
153
154/* PBC Board Control Register 1 bit definitions */
155#define PBC_BCTRL1_ERST 0x0001 /* Ethernet Reset */
156#define PBC_BCTRL1_URST 0x0002 /* Reset External UART controller */
157#define PBC_BCTRL1_FRST 0x0004 /* FEC Reset */
158#define PBC_BCTRL1_ESLEEP 0x0010 /* Enable ethernet Sleep */
159#define PBC_BCTRL1_LCDON 0x0800 /* Enable the LCD */
160
161/* PBC Board Control Register 2 bit definitions */
162#define PBC_BCTRL2_VCC_EN 0x0004 /* Enable VCC */
163#define PBC_BCTRL2_VPP_EN 0x0008 /* Enable Vpp */
164#define PBC_BCTRL2_ATAFEC_EN 0X0010
165#define PBC_BCTRL2_ATAFEC_SEL 0X0020
166#define PBC_BCTRL2_ATA_EN 0X0040
167#define PBC_BCTRL2_IRDA_SD 0X0080
168#define PBC_BCTRL2_IRDA_EN 0X0100
169#define PBC_BCTRL2_CCTL10 0X0200
170#define PBC_BCTRL2_CCTL11 0X0400
171
172/* PBC Board Control Register 3 bit definitions */
173#define PBC_BCTRL3_HSH_EN 0X0020
174#define PBC_BCTRL3_FSH_MOD 0X0040
175#define PBC_BCTRL3_OTG_HS_EN 0X0080
176#define PBC_BCTRL3_OTG_VBUS_EN 0X0100
177#define PBC_BCTRL3_FSH_VBUS_EN 0X0200
178#define PBC_BCTRL3_USB_OTG_ON 0X0800
179#define PBC_BCTRL3_USB_FSH_ON 0X1000
180
181/* PBC Board Control Register 4 bit definitions */
182#define PBC_BCTRL4_REGEN_SEL 0X0001
183#define PBC_BCTRL4_USER_OFF 0X0002
184#define PBC_BCTRL4_VIB_EN 0X0004
185#define PBC_BCTRL4_PWRGT1_EN 0X0008
186#define PBC_BCTRL4_PWRGT2_EN 0X0010
187#define PBC_BCTRL4_STDBY_PRI 0X0020
188
189#ifndef __ASSEMBLY__
190/*
191 * Enumerations for SD cards and memory stick card. This corresponds to
192 * the card EN bits in the IMR: SD1_EN | MS_EN | SD3_EN | SD2_EN.
193 */
194enum mxc_card_no {
195 MXC_CARD_SD2 = 0,
196 MXC_CARD_SD3,
197 MXC_CARD_MS,
198 MXC_CARD_SD1,
199 MXC_CARD_MIN = MXC_CARD_SD2,
200 MXC_CARD_MAX = MXC_CARD_SD1,
201};
202#endif
203
204#define MXC_CPLD_VER_1_50 0x01
205
206/*
207 * PBC BSTAT Register bit definitions
208 */
209#define PBC_BSTAT_PRI_INT 0X0001
210#define PBC_BSTAT_USB_BYP 0X0002
211#define PBC_BSTAT_ATA_IOCS16 0X0004
212#define PBC_BSTAT_ATA_CBLID 0X0008
213#define PBC_BSTAT_ATA_DASP 0X0010
214#define PBC_BSTAT_PWR_RDY 0X0020
215#define PBC_BSTAT_SD3_WP 0X0100
216#define PBC_BSTAT_SD2_WP 0X0200
217#define PBC_BSTAT_SD1_WP 0X0400
218#define PBC_BSTAT_SD3_DET 0X0800
219#define PBC_BSTAT_SD2_DET 0X1000
220#define PBC_BSTAT_SD1_DET 0X2000
221#define PBC_BSTAT_MS_DET 0X4000
222#define PBC_BSTAT_SD3_DET_BIT 11
223#define PBC_BSTAT_SD2_DET_BIT 12
224#define PBC_BSTAT_SD1_DET_BIT 13
225#define PBC_BSTAT_MS_DET_BIT 14
226#define MXC_BSTAT_BIT(n) ((n == MXC_CARD_SD2) ? PBC_BSTAT_SD2_DET : \
227 ((n == MXC_CARD_SD3) ? PBC_BSTAT_SD3_DET : \
228 ((n == MXC_CARD_SD1) ? PBC_BSTAT_SD1_DET : \
229 ((n == MXC_CARD_MS) ? PBC_BSTAT_MS_DET : \
230 0x0))))
231
232/*
233 * PBC UART Control Register bit definitions
234 */
235#define PBC_UCTRL_DCE_DCD 0X0001
236#define PBC_UCTRL_DCE_DSR 0X0002
237#define PBC_UCTRL_DCE_RI 0X0004
238#define PBC_UCTRL_DTE_DTR 0X0100
239
240/*
241 * PBC UART Status Register bit definitions
242 */
243#define PBC_USTAT_DTE_DCD 0X0001
244#define PBC_USTAT_DTE_DSR 0X0002
245#define PBC_USTAT_DTE_RI 0X0004
246#define PBC_USTAT_DCE_DTR 0X0100
247
248/*
249 * PBC Interupt mask register bit definitions
250 */
251#define PBC_INTR_SD3_R_EN_BIT 4
252#define PBC_INTR_SD2_R_EN_BIT 0
253#define PBC_INTR_SD1_R_EN_BIT 6
254#define PBC_INTR_MS_R_EN_BIT 5
255#define PBC_INTR_SD3_EN_BIT 13
256#define PBC_INTR_SD2_EN_BIT 12
257#define PBC_INTR_MS_EN_BIT 14
258#define PBC_INTR_SD1_EN_BIT 15
259
260#define PBC_INTR_SD2_R_EN 0x0001
261#define PBC_INTR_LOW_BAT 0X0002
262#define PBC_INTR_OTG_FSOVER 0X0004
263#define PBC_INTR_FSH_OVER 0X0008
264#define PBC_INTR_SD3_R_EN 0x0010
265#define PBC_INTR_MS_R_EN 0x0020
266#define PBC_INTR_SD1_R_EN 0x0040
267#define PBC_INTR_FEC_INT 0X0080
268#define PBC_INTR_ENET_INT 0X0100
269#define PBC_INTR_OTGFS_INT 0X0200
270#define PBC_INTR_XUART_INT 0X0400
271#define PBC_INTR_CCTL12 0X0800
272#define PBC_INTR_SD2_EN 0x1000
273#define PBC_INTR_SD3_EN 0x2000
274#define PBC_INTR_MS_EN 0x4000
275#define PBC_INTR_SD1_EN 0x8000
276
277
278
279/* For interrupts like xuart, enet etc */
280#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX27_PIN_TIN)
281#define MXC_MAX_EXP_IO_LINES 16
282
283/*
284 * This corresponds to PBC_INTMASK_SET_REG at offset 0x38.
285 *
286 */
287#define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 1)
288#define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2)
289#define EXPIO_INT_FSH_OVR (MXC_EXP_IO_BASE + 3)
290#define EXPIO_INT_RES4 (MXC_EXP_IO_BASE + 4)
291#define EXPIO_INT_RES5 (MXC_EXP_IO_BASE + 5)
292#define EXPIO_INT_RES6 (MXC_EXP_IO_BASE + 6)
293#define EXPIO_INT_FEC (MXC_EXP_IO_BASE + 7)
294#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8)
295#define EXPIO_INT_OTG_FS_INT (MXC_EXP_IO_BASE + 9)
296#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
297#define EXPIO_INT_CCTL12_INT (MXC_EXP_IO_BASE + 11)
298#define EXPIO_INT_SD2_EN (MXC_EXP_IO_BASE + 12)
299#define EXPIO_INT_SD3_EN (MXC_EXP_IO_BASE + 13)
300#define EXPIO_INT_MS_EN (MXC_EXP_IO_BASE + 14)
301#define EXPIO_INT_SD1_EN (MXC_EXP_IO_BASE + 15)
302
303/*
304 * This is System IRQ used by CS8900A for interrupt generation
305 * taken from platform.h
306 */
307#define CS8900AIRQ EXPIO_INT_ENET_INT
308/* This is I/O Base address used to access registers of CS8900A on MXC ADS */
309#define CS8900A_BASE_ADDRESS (PBC_CS8900A_IOBASE_REG + 0x300)
310
311#define MXC_PMIC_INT_LINE IOMUX_TO_IRQ(MX27_PIN_TOUT)
312
313/*
314* This is used to detect if the CPLD version is for mx27 evb board rev-a
315*/
316#define PBC_CPLD_VERSION_IS_REVA() \
317 ((__raw_readw(PBC_VERSION_REG) & \
318 (PBC_VERSION_ADS | PBC_VERSION_EVB_REVB))\
319 == 0)
320
321/* This is used to active or inactive ata signal in CPLD .
322 * It is dependent with hardware
323 */
324#define PBC_ATA_SIGNAL_ACTIVE() \
325 __raw_writew( \
326 PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
327 PBC_BCTRL2_CLEAR_REG)
328
329#define PBC_ATA_SIGNAL_INACTIVE() \
330 __raw_writew( \
331 PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
332 PBC_BCTRL2_SET_REG)
333
334#define MXC_BD_LED1 (1 << 5)
335#define MXC_BD_LED2 (1 << 6)
336#define MXC_BD_LED_ON(led) \
337 __raw_writew(led, PBC_BCTRL1_SET_REG)
338#define MXC_BD_LED_OFF(led) \
339 __raw_writew(led, PBC_BCTRL1_CLEAR_REG)
340
341/* to determine the correct external crystal reference */
342#define CKIH_27MHZ_BIT_SET (1 << 3)
343
344#endif /* __ASM_ARCH_MXC_BOARD_MX27ADS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27lite.h b/arch/arm/plat-mxc/include/mach/board-mx27lite.h
deleted file mode 100644
index ea87551d2736..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-mx27lite.h
+++ /dev/null
@@ -1,14 +0,0 @@
1/*
2 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_BOARD_MX27LITE_H__
12#define __ASM_ARCH_MXC_BOARD_MX27LITE_H__
13
14#endif /* __ASM_ARCH_MXC_BOARD_MX27LITE_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27pdk.h b/arch/arm/plat-mxc/include/mach/board-mx27pdk.h
deleted file mode 100644
index fec1bcfa9164..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-mx27pdk.h
+++ /dev/null
@@ -1,14 +0,0 @@
1/*
2 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_BOARD_MX27PDK_H__
12#define __ASM_ARCH_MXC_BOARD_MX27PDK_H__
13
14#endif /* __ASM_ARCH_MXC_BOARD_MX27PDK_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h b/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
deleted file mode 100644
index da92933a233b..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
+++ /dev/null
@@ -1,59 +0,0 @@
1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_BOARD_MX31_3DS_H__
12#define __ASM_ARCH_MXC_BOARD_MX31_3DS_H__
13
14/* Definitions for components on the Debug board */
15
16/* Base address of CPLD controller on the Debug board */
17#define DEBUG_BASE_ADDRESS CS5_IO_ADDRESS(CS5_BASE_ADDR)
18
19/* LAN9217 ethernet base address */
20#define LAN9217_BASE_ADDR CS5_BASE_ADDR
21
22/* CPLD config and interrupt base address */
23#define CPLD_ADDR (DEBUG_BASE_ADDRESS + 0x20000)
24
25/* LED switchs */
26#define CPLD_LED_REG (CPLD_ADDR + 0x00)
27/* buttons */
28#define CPLD_SWITCH_BUTTONS_REG (EXPIO_ADDR + 0x08)
29/* status, interrupt */
30#define CPLD_INT_STATUS_REG (CPLD_ADDR + 0x10)
31#define CPLD_INT_MASK_REG (CPLD_ADDR + 0x38)
32#define CPLD_INT_RESET_REG (CPLD_ADDR + 0x20)
33/* magic word for debug CPLD */
34#define CPLD_MAGIC_NUMBER1_REG (CPLD_ADDR + 0x40)
35#define CPLD_MAGIC_NUMBER2_REG (CPLD_ADDR + 0x48)
36/* CPLD code version */
37#define CPLD_CODE_VER_REG (CPLD_ADDR + 0x50)
38/* magic word for debug CPLD */
39#define CPLD_MAGIC_NUMBER3_REG (CPLD_ADDR + 0x58)
40/* module reset register */
41#define CPLD_MODULE_RESET_REG (CPLD_ADDR + 0x60)
42/* CPU ID and Personality ID */
43#define CPLD_MCU_BOARD_ID_REG (CPLD_ADDR + 0x68)
44
45/* CPLD IRQ line for external uart, external ethernet etc */
46#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
47
48#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
49#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
50
51#define EXPIO_INT_ENET (MXC_EXP_IO_BASE + 0)
52#define EXPIO_INT_XUART_A (MXC_EXP_IO_BASE + 1)
53#define EXPIO_INT_XUART_B (MXC_EXP_IO_BASE + 2)
54#define EXPIO_INT_BUTTON_A (MXC_EXP_IO_BASE + 3)
55#define EXPIO_INT_BUTTON_B (MXC_EXP_IO_BASE + 4)
56
57#define MXC_MAX_EXP_IO_LINES 16
58
59#endif /* __ASM_ARCH_MXC_BOARD_MX31_3DS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
deleted file mode 100644
index 095a199591c6..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-mx31ads.h
+++ /dev/null
@@ -1,117 +0,0 @@
1/*
2 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
12#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
13
14#include <mach/hardware.h>
15
16/* Base address of PBC controller */
17#define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT
18/* Offsets for the PBC Controller register */
19
20/* PBC Board status register offset */
21#define PBC_BSTAT 0x000002
22
23/* PBC Board control register 1 set address */
24#define PBC_BCTRL1_SET 0x000004
25
26/* PBC Board control register 1 clear address */
27#define PBC_BCTRL1_CLEAR 0x000006
28
29/* PBC Board control register 2 set address */
30#define PBC_BCTRL2_SET 0x000008
31
32/* PBC Board control register 2 clear address */
33#define PBC_BCTRL2_CLEAR 0x00000A
34
35/* PBC Board control register 3 set address */
36#define PBC_BCTRL3_SET 0x00000C
37
38/* PBC Board control register 3 clear address */
39#define PBC_BCTRL3_CLEAR 0x00000E
40
41/* PBC Board control register 4 set address */
42#define PBC_BCTRL4_SET 0x000010
43
44/* PBC Board control register 4 clear address */
45#define PBC_BCTRL4_CLEAR 0x000012
46
47/* PBC Board status register 1 */
48#define PBC_BSTAT1 0x000014
49
50/* PBC Board interrupt status register */
51#define PBC_INTSTATUS 0x000016
52
53/* PBC Board interrupt current status register */
54#define PBC_INTCURR_STATUS 0x000018
55
56/* PBC Interrupt mask register set address */
57#define PBC_INTMASK_SET 0x00001A
58
59/* PBC Interrupt mask register clear address */
60#define PBC_INTMASK_CLEAR 0x00001C
61
62/* External UART A */
63#define PBC_SC16C652_UARTA 0x010000
64
65/* External UART B */
66#define PBC_SC16C652_UARTB 0x010010
67
68/* Ethernet Controller IO base address */
69#define PBC_CS8900A_IOBASE 0x020000
70
71/* Ethernet Controller Memory base address */
72#define PBC_CS8900A_MEMBASE 0x021000
73
74/* Ethernet Controller DMA base address */
75#define PBC_CS8900A_DMABASE 0x022000
76
77/* External chip select 0 */
78#define PBC_XCS0 0x040000
79
80/* LCD Display enable */
81#define PBC_LCD_EN_B 0x060000
82
83/* Code test debug enable */
84#define PBC_CODE_B 0x070000
85
86/* PSRAM memory select */
87#define PBC_PSRAM_B 0x5000000
88
89#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS)
90#define PBC_INTCURR_STATUS_REG (PBC_INTCURR_STATUS + PBC_BASE_ADDRESS)
91#define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
92#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
93#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
94
95#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
96#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
97
98#define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 0)
99#define EXPIO_INT_PB_IRQ (MXC_EXP_IO_BASE + 1)
100#define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2)
101#define EXPIO_INT_FSH_OVR (MXC_EXP_IO_BASE + 3)
102#define EXPIO_INT_RES4 (MXC_EXP_IO_BASE + 4)
103#define EXPIO_INT_RES5 (MXC_EXP_IO_BASE + 5)
104#define EXPIO_INT_RES6 (MXC_EXP_IO_BASE + 6)
105#define EXPIO_INT_RES7 (MXC_EXP_IO_BASE + 7)
106#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8)
107#define EXPIO_INT_OTG_FS_INT (MXC_EXP_IO_BASE + 9)
108#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
109#define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11)
110#define EXPIO_INT_SYNTH_IRQ (MXC_EXP_IO_BASE + 12)
111#define EXPIO_INT_CE_INT1 (MXC_EXP_IO_BASE + 13)
112#define EXPIO_INT_CE_INT2 (MXC_EXP_IO_BASE + 14)
113#define EXPIO_INT_RES15 (MXC_EXP_IO_BASE + 15)
114
115#define MXC_MAX_EXP_IO_LINES 16
116
117#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lilly.h b/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
index eb5a5024622e..0df71bfefbb1 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
@@ -31,7 +31,7 @@ enum mx31lilly_boards {
31 31
32/* 32/*
33 * This CPU module needs a baseboard to work. After basic initializing 33 * This CPU module needs a baseboard to work. After basic initializing
34 * its own devices, it calls baseboard's init function. 34 * its own devices, it calls the baseboard's init function.
35 */ 35 */
36 36
37extern void mx31lilly_db_init(void); 37extern void mx31lilly_db_init(void);
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lite.h b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
index 2b2da0367578..c1ad0ae807cc 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31lite.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
@@ -32,7 +32,7 @@ enum mx31lite_boards {
32 32
33/* 33/*
34 * This CPU module needs a baseboard to work. After basic initializing 34 * This CPU module needs a baseboard to work. After basic initializing
35 * its own devices, it calls baseboard's init function. 35 * its own devices, it calls the baseboard's init function.
36 */ 36 */
37 37
38extern void mx31lite_db_init(void); 38extern void mx31lite_db_init(void);
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
index 36ff3cedee1a..de14543891cf 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
@@ -31,7 +31,7 @@ enum mx31moboard_boards {
31 31
32/* 32/*
33 * This CPU module needs a baseboard to work. After basic initializing 33 * This CPU module needs a baseboard to work. After basic initializing
34 * its own devices, it calls baseboard's init function. 34 * its own devices, it calls the baseboard's init function.
35 */ 35 */
36 36
37extern void mx31moboard_devboard_init(void); 37extern void mx31moboard_devboard_init(void);
diff --git a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h b/arch/arm/plat-mxc/include/mach/board-mx35pdk.h
deleted file mode 100644
index 383f1c04df06..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#ifndef __ASM_ARCH_MXC_BOARD_MX35PDK_H__
20#define __ASM_ARCH_MXC_BOARD_MX35PDK_H__
21
22#endif /* __ASM_ARCH_MXC_BOARD_MX35PDK_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm037.h b/arch/arm/plat-mxc/include/mach/board-pcm037.h
deleted file mode 100644
index 13411709b13a..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-pcm037.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * Copyright (C) 2008 Sascha Hauer, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#ifndef __ASM_ARCH_MXC_BOARD_PCM037_H__
20#define __ASM_ARCH_MXC_BOARD_PCM037_H__
21
22#endif /* __ASM_ARCH_MXC_BOARD_PCM037_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm038.h b/arch/arm/plat-mxc/include/mach/board-pcm038.h
index 410f9786ed22..6f371e35753d 100644
--- a/arch/arm/plat-mxc/include/mach/board-pcm038.h
+++ b/arch/arm/plat-mxc/include/mach/board-pcm038.h
@@ -22,7 +22,7 @@
22#ifndef __ASSEMBLY__ 22#ifndef __ASSEMBLY__
23/* 23/*
24 * This CPU module needs a baseboard to work. After basic initializing 24 * This CPU module needs a baseboard to work. After basic initializing
25 * its own devices, it calls baseboard's init function. 25 * its own devices, it calls the baseboard's init function.
26 * TODO: Add your own baseboard init function and call it from 26 * TODO: Add your own baseboard init function and call it from
27 * inside pcm038_init(). 27 * inside pcm038_init().
28 * 28 *
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm043.h b/arch/arm/plat-mxc/include/mach/board-pcm043.h
deleted file mode 100644
index 1ac4e1682e5c..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-pcm043.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * Copyright (C) 2008 Sascha Hauer, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#ifndef __ASM_ARCH_MXC_BOARD_PCM043_H__
20#define __ASM_ARCH_MXC_BOARD_PCM043_H__
21
22#endif /* __ASM_ARCH_MXC_BOARD_PCM043_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-qong.h b/arch/arm/plat-mxc/include/mach/board-qong.h
deleted file mode 100644
index 6d88c7af4b23..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-qong.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/*
2 * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_BOARD_QONG_H__
12#define __ASM_ARCH_MXC_BOARD_QONG_H__
13
14/* NOR FLASH */
15#define QONG_NOR_SIZE (128*1024*1024)
16
17#endif /* __ASM_ARCH_MXC_BOARD_QONG_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
new file mode 100644
index 000000000000..05c8d3f0a08f
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -0,0 +1,42 @@
1/*
2 * Copyright (C) 2009-2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <linux/kernel.h>
10#include <linux/platform_device.h>
11#include <linux/init.h>
12
13struct platform_device *imx_add_platform_device(const char *name, int id,
14 const struct resource *res, unsigned int num_resources,
15 const void *data, size_t size_data);
16
17#include <mach/i2c.h>
18struct platform_device *__init imx_add_imx_i2c(int id,
19 resource_size_t iobase, resource_size_t iosize, int irq,
20 const struct imxi2c_platform_data *pdata);
21
22#include <mach/imx-uart.h>
23struct platform_device *__init imx_add_imx_uart_3irq(int id,
24 resource_size_t iobase, resource_size_t iosize,
25 resource_size_t irqrx, resource_size_t irqtx,
26 resource_size_t irqrts,
27 const struct imxuart_platform_data *pdata);
28struct platform_device *__init imx_add_imx_uart_1irq(int id,
29 resource_size_t iobase, resource_size_t iosize,
30 resource_size_t irq,
31 const struct imxuart_platform_data *pdata);
32
33#include <mach/mxc_nand.h>
34struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase,
35 int irq, const struct mxc_nand_platform_data *pdata);
36struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase,
37 int irq, const struct mxc_nand_platform_data *pdata);
38
39#include <mach/spi.h>
40struct platform_device *__init imx_add_spi_imx(int id,
41 resource_size_t iobase, resource_size_t iosize, int irq,
42 const struct spi_imx_master *pdata);
diff --git a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
deleted file mode 100644
index 7c4870bd5a21..000000000000
--- a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
+++ /dev/null
@@ -1,105 +0,0 @@
1/*
2 * linux/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
3 *
4 * i.MX DMA registration and IRQ dispatching
5 *
6 * Copyright 2006 Pavel Pisa <pisa@cmp.felk.cvut.cz>
7 * Copyright 2008 Juergen Beisert, <kernel@pengutronix.de>
8 * Copyright 2008 Sascha Hauer, <s.hauer@pengutronix.de>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
22 * MA 02110-1301, USA.
23 */
24
25#ifndef __ASM_ARCH_MXC_DMA_H
26#define __ASM_ARCH_MXC_DMA_H
27
28#define IMX_DMA_CHANNELS 16
29
30#define DMA_MODE_READ 0
31#define DMA_MODE_WRITE 1
32#define DMA_MODE_MASK 1
33
34#define MX1_DMA_REG(offset) MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR + (offset))
35
36/* DMA Interrupt Mask Register */
37#define MX1_DMA_DIMR MX1_DMA_REG(0x08)
38
39/* Channel Control Register */
40#define MX1_DMA_CCR(x) MX1_DMA_REG(0x8c + ((x) << 6))
41
42#define IMX_DMA_MEMSIZE_32 (0 << 4)
43#define IMX_DMA_MEMSIZE_8 (1 << 4)
44#define IMX_DMA_MEMSIZE_16 (2 << 4)
45#define IMX_DMA_TYPE_LINEAR (0 << 10)
46#define IMX_DMA_TYPE_2D (1 << 10)
47#define IMX_DMA_TYPE_FIFO (2 << 10)
48
49#define IMX_DMA_ERR_BURST (1 << 0)
50#define IMX_DMA_ERR_REQUEST (1 << 1)
51#define IMX_DMA_ERR_TRANSFER (1 << 2)
52#define IMX_DMA_ERR_BUFFER (1 << 3)
53#define IMX_DMA_ERR_TIMEOUT (1 << 4)
54
55int
56imx_dma_config_channel(int channel, unsigned int config_port,
57 unsigned int config_mem, unsigned int dmareq, int hw_chaining);
58
59void
60imx_dma_config_burstlen(int channel, unsigned int burstlen);
61
62int
63imx_dma_setup_single(int channel, dma_addr_t dma_address,
64 unsigned int dma_length, unsigned int dev_addr,
65 unsigned int dmamode);
66
67
68/*
69 * Use this flag as the dma_length argument to imx_dma_setup_sg()
70 * to create an endless running dma loop. The end of the scatterlist
71 * must be linked to the beginning for this to work.
72 */
73#define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
74
75int
76imx_dma_setup_sg(int channel, struct scatterlist *sg,
77 unsigned int sgcount, unsigned int dma_length,
78 unsigned int dev_addr, unsigned int dmamode);
79
80int
81imx_dma_setup_handlers(int channel,
82 void (*irq_handler) (int, void *),
83 void (*err_handler) (int, void *, int), void *data);
84
85int
86imx_dma_setup_progression_handler(int channel,
87 void (*prog_handler) (int, void*, struct scatterlist*));
88
89void imx_dma_enable(int channel);
90
91void imx_dma_disable(int channel);
92
93int imx_dma_request(int channel, const char *name);
94
95void imx_dma_free(int channel);
96
97enum imx_dma_prio {
98 DMA_PRIO_HIGH = 0,
99 DMA_PRIO_MEDIUM = 1,
100 DMA_PRIO_LOW = 2
101};
102
103int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio);
104
105#endif /* _ASM_ARCH_MXC_DMA_H */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
index 3887f3fe29d4..15d59510f597 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 15 */
20 16
21#ifndef __MACH_IOMUX_MXC91231_H__ 17#ifndef __MACH_IOMUX_MXC91231_H__
diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h
index 5eba7e6785de..641b24618239 100644
--- a/arch/arm/plat-mxc/include/mach/mx1.h
+++ b/arch/arm/plat-mxc/include/mach/mx1.h
@@ -91,24 +91,24 @@
91#define MX1_SIM_DATA_INT 16 91#define MX1_SIM_DATA_INT 16
92#define MX1_RTC_INT 17 92#define MX1_RTC_INT 17
93#define MX1_RTC_SAMINT 18 93#define MX1_RTC_SAMINT 18
94#define MX1_UART2_MINT_PFERR 19 94#define MX1_INT_UART2PFERR 19
95#define MX1_UART2_MINT_RTS 20 95#define MX1_INT_UART2RTS 20
96#define MX1_UART2_MINT_DTR 21 96#define MX1_INT_UART2DTR 21
97#define MX1_UART2_MINT_UARTC 22 97#define MX1_INT_UART2UARTC 22
98#define MX1_UART2_MINT_TX 23 98#define MX1_INT_UART2TX 23
99#define MX1_UART2_MINT_RX 24 99#define MX1_INT_UART2RX 24
100#define MX1_UART1_MINT_PFERR 25 100#define MX1_INT_UART1PFERR 25
101#define MX1_UART1_MINT_RTS 26 101#define MX1_INT_UART1RTS 26
102#define MX1_UART1_MINT_DTR 27 102#define MX1_INT_UART1DTR 27
103#define MX1_UART1_MINT_UARTC 28 103#define MX1_INT_UART1UARTC 28
104#define MX1_UART1_MINT_TX 29 104#define MX1_INT_UART1TX 29
105#define MX1_UART1_MINT_RX 30 105#define MX1_INT_UART1RX 30
106#define MX1_VOICE_DAC_INT 31 106#define MX1_VOICE_DAC_INT 31
107#define MX1_VOICE_ADC_INT 32 107#define MX1_VOICE_ADC_INT 32
108#define MX1_PEN_DATA_INT 33 108#define MX1_PEN_DATA_INT 33
109#define MX1_PWM_INT 34 109#define MX1_PWM_INT 34
110#define MX1_SDHC_INT 35 110#define MX1_SDHC_INT 35
111#define MX1_I2C_INT 39 111#define MX1_INT_I2C 39
112#define MX1_CSPI_INT 41 112#define MX1_CSPI_INT 41
113#define MX1_SSI_TX_INT 42 113#define MX1_SSI_TX_INT 42
114#define MX1_SSI_TX_ERR_INT 43 114#define MX1_SSI_TX_ERR_INT 43
@@ -245,7 +245,7 @@
245#define PEN_DATA_INT MX1_PEN_DATA_INT 245#define PEN_DATA_INT MX1_PEN_DATA_INT
246#define PWM_INT MX1_PWM_INT 246#define PWM_INT MX1_PWM_INT
247#define SDHC_INT MX1_SDHC_INT 247#define SDHC_INT MX1_SDHC_INT
248#define I2C_INT MX1_I2C_INT 248#define I2C_INT MX1_INT_I2C
249#define CSPI_INT MX1_CSPI_INT 249#define CSPI_INT MX1_CSPI_INT
250#define SSI_TX_INT MX1_SSI_TX_INT 250#define SSI_TX_INT MX1_SSI_TX_INT
251#define SSI_TX_ERR_INT MX1_SSI_TX_ERR_INT 251#define SSI_TX_ERR_INT MX1_SSI_TX_ERR_INT
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index 7516f2949afe..2f2aad1032c1 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -11,6 +11,10 @@
11#define MX25_AVIC_BASE_ADDR_VIRT 0xfc400000 11#define MX25_AVIC_BASE_ADDR_VIRT 0xfc400000
12#define MX25_AVIC_SIZE SZ_1M 12#define MX25_AVIC_SIZE SZ_1M
13 13
14#define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000)
15#define MX25_I2C3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x84000)
16#define MX25_I2C2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x98000)
17#define MX25_CSPI1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa4000)
14#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000) 18#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000)
15 19
16#define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) 20#define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000)
@@ -30,7 +34,12 @@
30#define MX25_UART1_BASE_ADDR 0x43f90000 34#define MX25_UART1_BASE_ADDR 0x43f90000
31#define MX25_UART2_BASE_ADDR 0x43f94000 35#define MX25_UART2_BASE_ADDR 0x43f94000
32#define MX25_AUDMUX_BASE_ADDR 0x43fb0000 36#define MX25_AUDMUX_BASE_ADDR 0x43fb0000
37#define MX25_UART3_BASE_ADDR 0x5000c000
38#define MX25_UART4_BASE_ADDR 0x50008000
39#define MX25_UART5_BASE_ADDR 0x5002c000
33 40
41#define MX25_CSPI3_BASE_ADDR 0x50004000
42#define MX25_CSPI2_BASE_ADDR 0x50010000
34#define MX25_FEC_BASE_ADDR 0x50038000 43#define MX25_FEC_BASE_ADDR 0x50038000
35#define MX25_SSI2_BASE_ADDR 0x50014000 44#define MX25_SSI2_BASE_ADDR 0x50014000
36#define MX25_SSI1_BASE_ADDR 0x50034000 45#define MX25_SSI1_BASE_ADDR 0x50034000
@@ -41,14 +50,25 @@
41#define MX25_OTG_BASE_ADDR 0x53ff4000 50#define MX25_OTG_BASE_ADDR 0x53ff4000
42#define MX25_CSI_BASE_ADDR 0x53ff8000 51#define MX25_CSI_BASE_ADDR 0x53ff8000
43 52
44#define MX25_INT_SSI2 11 53#define MX25_INT_CSPI3 0
45#define MX25_INT_SSI1 12 54#define MX25_INT_I2C1 3
46#define MX25_INT_CSI 17 55#define MX25_INT_I2C2 4
47#define MX25_INT_DRYICE 25 56#define MX25_INT_UART4 5
48#define MX25_INT_NANDFC 33 57#define MX25_INT_I2C3 10
49#define MX25_INT_LCDC 39 58#define MX25_INT_SSI2 11
50#define MX25_INT_KPP 24 59#define MX25_INT_SSI1 12
51#define MX25_INT_FEC 57 60#define MX25_INT_CSPI2 13
61#define MX25_INT_CSPI1 14
62#define MX25_INT_CSI 17
63#define MX25_INT_UART3 18
64#define MX25_INT_KPP 24
65#define MX25_INT_DRYICE 25
66#define MX25_INT_UART2 32
67#define MX25_INT_NANDFC 33
68#define MX25_INT_LCDC 39
69#define MX25_INT_UART5 40
70#define MX25_INT_UART1 45
71#define MX25_INT_FEC 57
52 72
53#if defined(IMX_NEEDS_DEPRECATED_SYMBOLS) 73#if defined(IMX_NEEDS_DEPRECATED_SYMBOLS)
54#define UART1_BASE_ADDR MX25_UART1_BASE_ADDR 74#define UART1_BASE_ADDR MX25_UART1_BASE_ADDR
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index bae9cd75beee..a8ab2e02a8ca 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -48,7 +48,7 @@
48#define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000) 48#define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000)
49#define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000) 49#define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000)
50#define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000) 50#define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000)
51#define MX27_I2C_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000) 51#define MX27_I2C1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000)
52#define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000) 52#define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000)
53#define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000) 53#define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000)
54#define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000) 54#define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000)
@@ -150,7 +150,7 @@ static inline void mx27_setup_weimcs(size_t cs,
150#define MX27_INT_SDHC3 9 150#define MX27_INT_SDHC3 9
151#define MX27_INT_SDHC2 10 151#define MX27_INT_SDHC2 10
152#define MX27_INT_SDHC1 11 152#define MX27_INT_SDHC1 11
153#define MX27_INT_I2C 12 153#define MX27_INT_I2C1 12
154#define MX27_INT_SSI2 13 154#define MX27_INT_SSI2 13
155#define MX27_INT_SSI1 14 155#define MX27_INT_SSI1 14
156#define MX27_INT_CSPI2 15 156#define MX27_INT_CSPI2 15
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index fb90e119c2b5..afee3ab9d62e 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -23,7 +23,7 @@
23#define MX31_ETB_SLOT4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x10000) 23#define MX31_ETB_SLOT4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x10000)
24#define MX31_ETB_SLOT5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x14000) 24#define MX31_ETB_SLOT5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x14000)
25#define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000) 25#define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000)
26#define MX31_I2C_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000) 26#define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000)
27#define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000) 27#define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000)
28#define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000) 28#define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000)
29#define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000) 29#define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000)
@@ -145,7 +145,7 @@ static inline void mx31_setup_weimcs(size_t cs,
145#define MX31_INT_FIRI 7 145#define MX31_INT_FIRI 7
146#define MX31_INT_MMC_SDHC2 8 146#define MX31_INT_MMC_SDHC2 8
147#define MX31_INT_MMC_SDHC1 9 147#define MX31_INT_MMC_SDHC1 9
148#define MX31_INT_I2C 10 148#define MX31_INT_I2C1 10
149#define MX31_INT_SSI2 11 149#define MX31_INT_SSI2 11
150#define MX31_INT_SSI1 12 150#define MX31_INT_SSI1 12
151#define MX31_INT_CSPI2 13 151#define MX31_INT_CSPI2 13
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index 526a55842ae5..cda60c715127 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -18,7 +18,7 @@
18#define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000) 18#define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000)
19#define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000) 19#define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000)
20#define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000) 20#define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000)
21#define MX35_I2C_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000) 21#define MX35_I2C1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000)
22#define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000) 22#define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000)
23#define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000) 23#define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000)
24#define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000) 24#define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000)
@@ -123,7 +123,7 @@
123#define MX35_INT_MMC_SDHC1 7 123#define MX35_INT_MMC_SDHC1 7
124#define MX35_INT_MMC_SDHC2 8 124#define MX35_INT_MMC_SDHC2 8
125#define MX35_INT_MMC_SDHC3 9 125#define MX35_INT_MMC_SDHC3 9
126#define MX35_INT_I2C 10 126#define MX35_INT_I2C1 10
127#define MX35_INT_SSI1 11 127#define MX35_INT_SSI1 11
128#define MX35_INT_SSI2 12 128#define MX35_INT_SSI2 12
129#define MX35_INT_CSPI2 13 129#define MX35_INT_CSPI2 13
diff --git a/arch/arm/plat-mxc/include/mach/mx3_camera.h b/arch/arm/plat-mxc/include/mach/mx3_camera.h
index 36d7ff27b5e2..f226ee3777e1 100644
--- a/arch/arm/plat-mxc/include/mach/mx3_camera.h
+++ b/arch/arm/plat-mxc/include/mach/mx3_camera.h
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */ 15 */
20 16
21#ifndef _MX3_CAMERA_H_ 17#ifndef _MX3_CAMERA_H_
diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h
index 5182b986b785..0ca3101ebf36 100644
--- a/arch/arm/plat-mxc/include/mach/mxc91231.h
+++ b/arch/arm/plat-mxc/include/mach/mxc91231.h
@@ -13,10 +13,6 @@
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */ 16 */
21#ifndef __MACH_MXC91231_H__ 17#ifndef __MACH_MXC91231_H__
22#define __MACH_MXC91231_H__ 18#define __MACH_MXC91231_H__
diff --git a/arch/arm/plat-mxc/include/mach/mxc_nand.h b/arch/arm/plat-mxc/include/mach/mxc_nand.h
index 2d74748c5db7..04c0d060d814 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_nand.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_nand.h
@@ -23,9 +23,9 @@
23#include <linux/mtd/partitions.h> 23#include <linux/mtd/partitions.h>
24 24
25struct mxc_nand_platform_data { 25struct mxc_nand_platform_data {
26 int width; /* data bus width in bytes */ 26 unsigned int width; /* data bus width in bytes */
27 int hw_ecc:1; /* 0 if supress hardware ECC */ 27 unsigned int hw_ecc:1; /* 0 if supress hardware ECC */
28 int flash_bbt:1; /* set to 1 to use a flash based bbt */ 28 unsigned int flash_bbt:1; /* set to 1 to use a flash based bbt */
29 struct mtd_partition *parts; /* partition table */ 29 struct mtd_partition *parts; /* partition table */
30 int nr_parts; /* size of parts */ 30 int nr_parts; /* size of parts */
31}; 31};
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
index ef00199568de..4acd1143a9bd 100644
--- a/arch/arm/plat-mxc/include/mach/system.h
+++ b/arch/arm/plat-mxc/include/mach/system.h
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 15 */
20 16
21#ifndef __ASM_ARCH_MXC_SYSTEM_H__ 17#ifndef __ASM_ARCH_MXC_SYSTEM_H__
diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h
index 024416ed11cd..2d9624697cc9 100644
--- a/arch/arm/plat-mxc/include/mach/timex.h
+++ b/arch/arm/plat-mxc/include/mach/timex.h
@@ -11,10 +11,6 @@
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */ 14 */
19 15
20#ifndef __ASM_ARCH_MXC_TIMEX_H__ 16#ifndef __ASM_ARCH_MXC_TIMEX_H__
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index b6d3d0fddc48..d9bd37e4667a 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -13,10 +13,6 @@
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */ 16 */
21#ifndef __ASM_ARCH_MXC_UNCOMPRESS_H__ 17#ifndef __ASM_ARCH_MXC_UNCOMPRESS_H__
22#define __ASM_ARCH_MXC_UNCOMPRESS_H__ 18#define __ASM_ARCH_MXC_UNCOMPRESS_H__
diff --git a/arch/arm/plat-mxc/include/mach/vmalloc.h b/arch/arm/plat-mxc/include/mach/vmalloc.h
index 44243a278434..ef6379c474be 100644
--- a/arch/arm/plat-mxc/include/mach/vmalloc.h
+++ b/arch/arm/plat-mxc/include/mach/vmalloc.h
@@ -11,10 +11,6 @@
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */ 14 */
19 15
20#ifndef __ASM_ARCH_MXC_VMALLOC_H__ 16#ifndef __ASM_ARCH_MXC_VMALLOC_H__
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