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authorRussell King <rmk+kernel@arm.linux.org.uk>2010-10-19 17:06:36 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-10-19 17:06:36 -0400
commit809b4e00baf006a990a73329ba381d536c6fa277 (patch)
treee949e0efd019d6f932537aba762792b07a84351c /arch/arm/plat-mxc/include/mach
parenta0a55682b83fd5f012afadcf415b030d7424ae68 (diff)
parent79a94c3538bda6869d7bb150b5e02dd3a72314dd (diff)
Merge branch 'devel-stable' into devel
Diffstat (limited to 'arch/arm/plat-mxc/include/mach')
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31ads.h33
-rw-r--r--arch/arm/plat-mxc/include/mach/common.h1
-rw-r--r--arch/arm/plat-mxc/include/mach/devices-common.h112
-rw-r--r--arch/arm/plat-mxc/include/mach/esdhc.h16
-rw-r--r--arch/arm/plat-mxc/include/mach/eukrea-baseboards.h5
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx51.h120
-rw-r--r--arch/arm/plat-mxc/include/mach/iram.h41
-rw-r--r--arch/arm/plat-mxc/include/mach/mx21.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/mx25.h17
-rw-r--r--arch/arm/plat-mxc/include/mach/mx27.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/mx31.h11
-rw-r--r--arch/arm/plat-mxc/include/mach/mx35.h38
-rw-r--r--arch/arm/plat-mxc/include/mach/mx3x.h23
-rw-r--r--arch/arm/plat-mxc/include/mach/mx51.h657
-rw-r--r--arch/arm/plat-mxc/include/mach/system.h32
-rw-r--r--arch/arm/plat-mxc/include/mach/uncompress.h1
16 files changed, 666 insertions, 445 deletions
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
new file mode 100644
index 000000000000..94b60dd47137
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
@@ -0,0 +1,33 @@
1/*
2 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
12#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
13
14#include <mach/hardware.h>
15
16/*
17 * These symbols are used by drivers/net/cs89x0.c.
18 * This is ugly as hell, but we have to provide them until
19 * someone fixed the driver.
20 */
21
22/* Base address of PBC controller */
23#define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT
24/* Offsets for the PBC Controller register */
25
26/* Ethernet Controller IO base address */
27#define PBC_CS8900A_IOBASE 0x020000
28
29#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
30
31#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8)
32
33#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 2941472582d2..7a1e1f89ff09 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -32,6 +32,7 @@ extern void mx31_init_irq(void);
32extern void mx35_init_irq(void); 32extern void mx35_init_irq(void);
33extern void mx51_init_irq(void); 33extern void mx51_init_irq(void);
34extern void mxc91231_init_irq(void); 34extern void mxc91231_init_irq(void);
35extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq);
35extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); 36extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int);
36extern int mx1_clocks_init(unsigned long fref); 37extern int mx1_clocks_init(unsigned long fref);
37extern int mx21_clocks_init(unsigned long lref, unsigned long fref); 38extern int mx21_clocks_init(unsigned long lref, unsigned long fref);
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index c5f68c587309..86d7575a564d 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -14,47 +14,105 @@ struct platform_device *imx_add_platform_device(const char *name, int id,
14 const struct resource *res, unsigned int num_resources, 14 const struct resource *res, unsigned int num_resources,
15 const void *data, size_t size_data); 15 const void *data, size_t size_data);
16 16
17#if defined (CONFIG_CAN_FLEXCAN) || defined (CONFIG_CAN_FLEXCAN_MODULE) 17#include <linux/fec.h>
18struct imx_fec_data {
19 resource_size_t iobase;
20 resource_size_t irq;
21};
22struct platform_device *__init imx_add_fec(
23 const struct imx_fec_data *data,
24 const struct fec_platform_data *pdata);
25
18#include <linux/can/platform/flexcan.h> 26#include <linux/can/platform/flexcan.h>
19struct platform_device *__init imx_add_flexcan(int id, 27struct platform_device *__init imx_add_flexcan(int id,
20 resource_size_t iobase, resource_size_t iosize, 28 resource_size_t iobase, resource_size_t iosize,
21 resource_size_t irq, 29 resource_size_t irq,
22 const struct flexcan_platform_data *pdata); 30 const struct flexcan_platform_data *pdata);
23#else
24/* the ifdef can be removed once the flexcan driver has been merged */
25struct flexcan_platform_data;
26static inline struct platform_device *__init imx_add_flexcan(int id,
27 resource_size_t iobase, resource_size_t iosize,
28 resource_size_t irq,
29 const struct flexcan_platform_data *pdata)
30{
31 return NULL;
32}
33#endif
34 31
35#include <mach/i2c.h> 32#include <mach/i2c.h>
36struct platform_device *__init imx_add_imx_i2c(int id, 33struct imx_imx_i2c_data {
37 resource_size_t iobase, resource_size_t iosize, int irq, 34 int id;
35 resource_size_t iobase;
36 resource_size_t iosize;
37 resource_size_t irq;
38};
39struct platform_device *__init imx_add_imx_i2c(
40 const struct imx_imx_i2c_data *data,
38 const struct imxi2c_platform_data *pdata); 41 const struct imxi2c_platform_data *pdata);
39 42
43#include <mach/ssi.h>
44struct imx_imx_ssi_data {
45 int id;
46 resource_size_t iobase;
47 resource_size_t iosize;
48 resource_size_t irq;
49 resource_size_t dmatx0;
50 resource_size_t dmarx0;
51 resource_size_t dmatx1;
52 resource_size_t dmarx1;
53};
54struct platform_device *__init imx_add_imx_ssi(
55 const struct imx_imx_ssi_data *data,
56 const struct imx_ssi_platform_data *pdata);
57
40#include <mach/imx-uart.h> 58#include <mach/imx-uart.h>
41struct platform_device *__init imx_add_imx_uart_3irq(int id, 59struct imx_imx_uart_3irq_data {
42 resource_size_t iobase, resource_size_t iosize, 60 int id;
43 resource_size_t irqrx, resource_size_t irqtx, 61 resource_size_t iobase;
44 resource_size_t irqrts, 62 resource_size_t iosize;
63 resource_size_t irqrx;
64 resource_size_t irqtx;
65 resource_size_t irqrts;
66};
67struct platform_device *__init imx_add_imx_uart_3irq(
68 const struct imx_imx_uart_3irq_data *data,
45 const struct imxuart_platform_data *pdata); 69 const struct imxuart_platform_data *pdata);
46struct platform_device *__init imx_add_imx_uart_1irq(int id, 70
47 resource_size_t iobase, resource_size_t iosize, 71struct imx_imx_uart_1irq_data {
48 resource_size_t irq, 72 int id;
73 resource_size_t iobase;
74 resource_size_t iosize;
75 resource_size_t irq;
76};
77struct platform_device *__init imx_add_imx_uart_1irq(
78 const struct imx_imx_uart_1irq_data *data,
49 const struct imxuart_platform_data *pdata); 79 const struct imxuart_platform_data *pdata);
50 80
51#include <mach/mxc_nand.h> 81#include <mach/mxc_nand.h>
52struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase, 82struct imx_mxc_nand_data {
53 int irq, const struct mxc_nand_platform_data *pdata); 83 /*
54struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase, 84 * id is traditionally 0, but -1 is more appropriate. We use -1 for new
55 int irq, const struct mxc_nand_platform_data *pdata); 85 * machines but don't change existing devices as the nand device usually
86 * appears in the kernel command line to pass its partitioning.
87 */
88 int id;
89 resource_size_t iobase;
90 resource_size_t iosize;
91 resource_size_t axibase;
92 resource_size_t irq;
93};
94struct platform_device *__init imx_add_mxc_nand(
95 const struct imx_mxc_nand_data *data,
96 const struct mxc_nand_platform_data *pdata);
56 97
57#include <mach/spi.h> 98#include <mach/spi.h>
58struct platform_device *__init imx_add_spi_imx(int id, 99struct imx_spi_imx_data {
59 resource_size_t iobase, resource_size_t iosize, int irq, 100 const char *devid;
101 int id;
102 resource_size_t iobase;
103 resource_size_t iosize;
104 int irq;
105};
106struct platform_device *__init imx_add_spi_imx(
107 const struct imx_spi_imx_data *data,
60 const struct spi_imx_master *pdata); 108 const struct spi_imx_master *pdata);
109
110#include <mach/esdhc.h>
111struct imx_esdhc_imx_data {
112 int id;
113 resource_size_t iobase;
114 resource_size_t irq;
115};
116struct platform_device *__init imx_add_esdhc(
117 const struct imx_esdhc_imx_data *data,
118 const struct esdhc_platform_data *pdata);
diff --git a/arch/arm/plat-mxc/include/mach/esdhc.h b/arch/arm/plat-mxc/include/mach/esdhc.h
new file mode 100644
index 000000000000..a48a9aaa56b1
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/esdhc.h
@@ -0,0 +1,16 @@
1/*
2 * Copyright 2010 Wolfram Sang <w.sang@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; version 2
7 * of the License.
8 */
9
10#ifndef __ASM_ARCH_IMX_ESDHC_H
11#define __ASM_ARCH_IMX_ESDHC_H
12
13struct esdhc_platform_data {
14 unsigned int wp_gpio; /* write protect pin */
15};
16#endif /* __ASM_ARCH_IMX_ESDHC_H */
diff --git a/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h b/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h
index 656acb45d434..a21d3313f994 100644
--- a/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h
+++ b/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h
@@ -28,19 +28,22 @@
28 * its own devices, it calls baseboard's init function. 28 * its own devices, it calls baseboard's init function.
29 * TODO: Add your own baseboard init function and call it from 29 * TODO: Add your own baseboard init function and call it from
30 * inside eukrea_cpuimx25_init() eukrea_cpuimx27_init() 30 * inside eukrea_cpuimx25_init() eukrea_cpuimx27_init()
31 * eukrea_cpuimx35_init() or eukrea_cpuimx51_init(). 31 * eukrea_cpuimx35_init() eukrea_cpuimx51_init()
32 * or eukrea_cpuimx51sd_init().
32 * 33 *
33 * This example here is for the development board. Refer 34 * This example here is for the development board. Refer
34 * mach-mx25/eukrea_mbimxsd-baseboard.c for cpuimx25 35 * mach-mx25/eukrea_mbimxsd-baseboard.c for cpuimx25
35 * mach-imx/eukrea_mbimx27-baseboard.c for cpuimx27 36 * mach-imx/eukrea_mbimx27-baseboard.c for cpuimx27
36 * mach-mx3/eukrea_mbimxsd-baseboard.c for cpuimx35 37 * mach-mx3/eukrea_mbimxsd-baseboard.c for cpuimx35
37 * mach-mx5/eukrea_mbimx51-baseboard.c for cpuimx51 38 * mach-mx5/eukrea_mbimx51-baseboard.c for cpuimx51
39 * mach-mx5/eukrea_mbimxsd-baseboard.c for cpuimx51sd
38 */ 40 */
39 41
40extern void eukrea_mbimxsd25_baseboard_init(void); 42extern void eukrea_mbimxsd25_baseboard_init(void);
41extern void eukrea_mbimx27_baseboard_init(void); 43extern void eukrea_mbimx27_baseboard_init(void);
42extern void eukrea_mbimxsd35_baseboard_init(void); 44extern void eukrea_mbimxsd35_baseboard_init(void);
43extern void eukrea_mbimx51_baseboard_init(void); 45extern void eukrea_mbimx51_baseboard_init(void);
46extern void eukrea_mbimxsd51_baseboard_init(void);
44 47
45#endif 48#endif
46 49
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index 21bfa46785bb..e46b1c2836d4 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -45,6 +45,18 @@ typedef enum iomux_config {
45 PAD_CTL_PKE | PAD_CTL_HYS) 45 PAD_CTL_PKE | PAD_CTL_HYS)
46#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \ 46#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \
47 PAD_CTL_SRE_FAST) 47 PAD_CTL_SRE_FAST)
48#define MX51_ECSPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
49 PAD_CTL_SRE_FAST)
50#define MX51_SDHCI_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP | \
51 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_SRE_FAST | \
52 PAD_CTL_DVS)
53
54#define MX51_PAD_CTRL_1 (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
55 PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_HYS)
56#define MX51_PAD_CTRL_2 (PAD_CTL_HYS | PAD_CTL_PKE)
57#define MX51_PAD_CTRL_3 (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
58#define MX51_PAD_CTRL_4 (PAD_CTL_DVS | PAD_CTL_HYS | PAD_CTL_PKE)
59#define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
48 60
49/* 61/*
50 * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode> 62 * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
@@ -106,14 +118,20 @@ typedef enum iomux_config {
106#define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL) 118#define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL)
107#define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL) 119#define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL)
108#define MX51_PAD_EIM_EB2__GPIO_2_22 IOMUX_PAD(0x468, 0x0d4, 1, 0x0, 0, NO_PAD_CTRL) 120#define MX51_PAD_EIM_EB2__GPIO_2_22 IOMUX_PAD(0x468, 0x0d4, 1, 0x0, 0, NO_PAD_CTRL)
121#define MX51_PAD_EIM_EB2__FEC_MDIO IOMUX_PAD(0x468, 0x0d4, 3, 0x0, 0, MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP)
109#define MX51_PAD_EIM_EB3__GPIO_2_23 IOMUX_PAD(0x46c, 0x0d8, 1, 0x0, 0, NO_PAD_CTRL) 122#define MX51_PAD_EIM_EB3__GPIO_2_23 IOMUX_PAD(0x46c, 0x0d8, 1, 0x0, 0, NO_PAD_CTRL)
123#define MX51_PAD_EIM_EB3__FEC_RDAT1 IOMUX_PAD(0x46c, 0x0d8, 3, 0x0, 0, MX51_PAD_CTRL_2)
110#define MX51_PAD_EIM_OE__GPIO_2_24 IOMUX_PAD(0x470, 0x0dc, 1, 0x0, 0, NO_PAD_CTRL) 124#define MX51_PAD_EIM_OE__GPIO_2_24 IOMUX_PAD(0x470, 0x0dc, 1, 0x0, 0, NO_PAD_CTRL)
111#define MX51_PAD_EIM_CS0__GPIO_2_25 IOMUX_PAD(0x474, 0x0e0, 1, 0x0, 0, NO_PAD_CTRL) 125#define MX51_PAD_EIM_CS0__GPIO_2_25 IOMUX_PAD(0x474, 0x0e0, 1, 0x0, 0, NO_PAD_CTRL)
112#define MX51_PAD_EIM_CS1__GPIO_2_26 IOMUX_PAD(0x478, 0x0e4, 1, 0x0, 0, NO_PAD_CTRL) 126#define MX51_PAD_EIM_CS1__GPIO_2_26 IOMUX_PAD(0x478, 0x0e4, 1, 0x0, 0, NO_PAD_CTRL)
113#define MX51_PAD_EIM_CS2__GPIO_2_27 IOMUX_PAD(0x47c, 0x0e8, 1, 0x0, 0, NO_PAD_CTRL) 127#define MX51_PAD_EIM_CS2__GPIO_2_27 IOMUX_PAD(0x47c, 0x0e8, 1, 0x0, 0, NO_PAD_CTRL)
128#define MX51_PAD_EIM_CS2__FEC_RDAT2 IOMUX_PAD(0x47c, 0x0e8, 3, 0x0, 0, MX51_PAD_CTRL_2)
114#define MX51_PAD_EIM_CS3__GPIO_2_28 IOMUX_PAD(0x480, 0x0ec, 1, 0x0, 0, NO_PAD_CTRL) 129#define MX51_PAD_EIM_CS3__GPIO_2_28 IOMUX_PAD(0x480, 0x0ec, 1, 0x0, 0, NO_PAD_CTRL)
130#define MX51_PAD_EIM_CS3__FEC_RDAT3 IOMUX_PAD(0x480, 0x0ec, 3, 0x0, 0, MX51_PAD_CTRL_2)
115#define MX51_PAD_EIM_CS4__GPIO_2_29 IOMUX_PAD(0x484, 0x0f0, 1, 0x0, 0, NO_PAD_CTRL) 131#define MX51_PAD_EIM_CS4__GPIO_2_29 IOMUX_PAD(0x484, 0x0f0, 1, 0x0, 0, NO_PAD_CTRL)
132#define MX51_PAD_EIM_CS4__FEC_RX_ER IOMUX_PAD(0x484, 0x0f0, 3, 0x0, 0, MX51_PAD_CTRL_2)
116#define MX51_PAD_EIM_CS5__GPIO_2_30 IOMUX_PAD(0x488, 0x0f4, 1, 0x0, 0, NO_PAD_CTRL) 133#define MX51_PAD_EIM_CS5__GPIO_2_30 IOMUX_PAD(0x488, 0x0f4, 1, 0x0, 0, NO_PAD_CTRL)
134#define MX51_PAD_EIM_CS5__FEC_CRS IOMUX_PAD(0x488, 0x0f4, 3, 0x0, 0, MX51_PAD_CTRL_2)
117#define MX51_PAD_EIM_DTACK__GPIO_2_31 IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, NO_PAD_CTRL) 135#define MX51_PAD_EIM_DTACK__GPIO_2_31 IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, NO_PAD_CTRL)
118#define MX51_PAD_EIM_LBA__GPIO_3_1 IOMUX_PAD(0x494, 0x0FC, 1, 0x0, 0, NO_PAD_CTRL) 136#define MX51_PAD_EIM_LBA__GPIO_3_1 IOMUX_PAD(0x494, 0x0FC, 1, 0x0, 0, NO_PAD_CTRL)
119#define MX51_PAD_EIM_CRE__GPIO_3_2 IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL) 137#define MX51_PAD_EIM_CRE__GPIO_3_2 IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL)
@@ -126,18 +144,32 @@ typedef enum iomux_config {
126#define MX51_PAD_NANDF_RB0__GPIO_3_8 IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL) 144#define MX51_PAD_NANDF_RB0__GPIO_3_8 IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL)
127#define MX51_PAD_NANDF_RB1__GPIO_3_9 IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL) 145#define MX51_PAD_NANDF_RB1__GPIO_3_9 IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL)
128#define MX51_PAD_NANDF_RB2__GPIO_3_10 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL) 146#define MX51_PAD_NANDF_RB2__GPIO_3_10 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL)
147#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, 0x0, 0, MX51_ECSPI_PAD_CTRL)
148#define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x0, 0, MX51_PAD_CTRL_2)
129#define MX51_PAD_NANDF_RB3__GPIO_3_11 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL) 149#define MX51_PAD_NANDF_RB3__GPIO_3_11 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL)
150#define MX51_PAD_NANDF_RB3__ECSPI2_MISO IOMUX_PAD(0x504, 0x128, 2, 0x0, 0, MX51_ECSPI_PAD_CTRL)
151#define MX51_PAD_NANDF_RB3__FEC_RXCLK IOMUX_PAD(0x504, 0x128, 1, 0x0, 0, MX51_PAD_CTRL_2)
152#define MX51_PAD_NANDF_RB6__FEC_RDAT0 IOMUX_PAD(0x5DC, 0x134, 1, 0x0, 0, MX51_PAD_CTRL_4)
153#define MX51_PAD_NANDF_RB7__FEC_TDAT0 IOMUX_PAD(0x5E0, 0x138, 1, 0x0, 0, MX51_PAD_CTRL_5)
130#define MX51_PAD_GPIO_NAND__GPIO_3_12 IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL) 154#define MX51_PAD_GPIO_NAND__GPIO_3_12 IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL)
131#define MX51_PAD_NANDF_CS0__GPIO_3_16 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL) 155#define MX51_PAD_NANDF_CS0__GPIO_3_16 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
132#define MX51_PAD_NANDF_CS1__GPIO_3_17 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL) 156#define MX51_PAD_NANDF_CS1__GPIO_3_17 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
133#define MX51_PAD_NANDF_CS2__GPIO_3_18 IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL) 157#define MX51_PAD_NANDF_CS2__GPIO_3_18 IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
158#define MX51_PAD_NANDF_CS2__FEC_TX_ER IOMUX_PAD(0x520, 0x138, 2, 0x0, 0, MX51_PAD_CTRL_5)
134#define MX51_PAD_NANDF_CS3__GPIO_3_19 IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL) 159#define MX51_PAD_NANDF_CS3__GPIO_3_19 IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL)
160#define MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13C, 2, 0x0, 0, MX51_PAD_CTRL_5)
135#define MX51_PAD_NANDF_CS4__GPIO_3_20 IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL) 161#define MX51_PAD_NANDF_CS4__GPIO_3_20 IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL)
162#define MX51_PAD_NANDF_CS4__FEC_TDAT1 IOMUX_PAD(0x528, 0x140, 2, 0x0, 0, MX51_PAD_CTRL_5)
136#define MX51_PAD_NANDF_CS5__GPIO_3_21 IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL) 163#define MX51_PAD_NANDF_CS5__GPIO_3_21 IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL)
164#define MX51_PAD_NANDF_CS5__FEC_TDAT2 IOMUX_PAD(0x52C, 0x144, 2, 0x0, 0, MX51_PAD_CTRL_5)
137#define MX51_PAD_NANDF_CS6__GPIO_3_22 IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL) 165#define MX51_PAD_NANDF_CS6__GPIO_3_22 IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL)
166#define MX51_PAD_NANDF_CS6__FEC_TDAT3 IOMUX_PAD(0x530, 0x148, 2, 0x0, 0, MX51_PAD_CTRL_5)
138#define MX51_PAD_NANDF_CS7__GPIO_3_23 IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL) 167#define MX51_PAD_NANDF_CS7__GPIO_3_23 IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL)
168#define MX51_PAD_NANDF_CS7__FEC_TX_EN IOMUX_PAD(0x534, 0x14C, 1, 0x0, 0, MX51_PAD_CTRL_5)
139#define MX51_PAD_NANDF_RDY_INT__GPIO_3_24 IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL) 169#define MX51_PAD_NANDF_RDY_INT__GPIO_3_24 IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL)
170#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x0, 0, MX51_PAD_CTRL_4)
140#define MX51_PAD_NANDF_D15__GPIO_3_25 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL) 171#define MX51_PAD_NANDF_D15__GPIO_3_25 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL)
172#define MX51_PAD_NANDF_D15__ECSPI2_MOSI IOMUX_PAD(0x53C, 0x154, 2, 0x0, 0, MX51_ECSPI_PAD_CTRL)
141#define MX51_PAD_NANDF_D14__GPIO_3_26 IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL) 173#define MX51_PAD_NANDF_D14__GPIO_3_26 IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL)
142#define MX51_PAD_NANDF_D13__GPIO_3_27 IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL) 174#define MX51_PAD_NANDF_D13__GPIO_3_27 IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL)
143#define MX51_PAD_NANDF_D12__GPIO_3_28 IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL) 175#define MX51_PAD_NANDF_D12__GPIO_3_28 IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL)
@@ -185,15 +217,25 @@ typedef enum iomux_config {
185#define MX51_PAD_I2C1_CLK__HSI2C_CLK IOMUX_PAD(0x5E8, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL) 217#define MX51_PAD_I2C1_CLK__HSI2C_CLK IOMUX_PAD(0x5E8, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL)
186#define MX51_PAD_I2C1_DAT__GPIO_4_17 IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL) 218#define MX51_PAD_I2C1_DAT__GPIO_4_17 IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL)
187#define MX51_PAD_I2C1_DAT__HSI2C_DAT IOMUX_PAD(0x5EC, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL) 219#define MX51_PAD_I2C1_DAT__HSI2C_DAT IOMUX_PAD(0x5EC, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL)
220#define MX51_PAD_AUD3_BB_TXD__AUD3_BB_TXD IOMUX_PAD(0x5F0, 0x200, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL)
188#define MX51_PAD_AUD3_BB_TXD__GPIO_4_18 IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL) 221#define MX51_PAD_AUD3_BB_TXD__GPIO_4_18 IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL)
222#define MX51_PAD_AUD3_BB_RXD__AUD3_BB_RXD IOMUX_PAD(0x5F4, 0x204, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL)
189#define MX51_PAD_AUD3_BB_RXD__GPIO_4_19 IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL) 223#define MX51_PAD_AUD3_BB_RXD__GPIO_4_19 IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL)
224#define MX51_PAD_AUD3_BB_CK__AUD3_BB_CK IOMUX_PAD(0x5F8, 0x208, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL)
190#define MX51_PAD_AUD3_BB_CK__GPIO_4_20 IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL) 225#define MX51_PAD_AUD3_BB_CK__GPIO_4_20 IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL)
226#define MX51_PAD_AUD3_BB_FS__AUD3_BB_FS IOMUX_PAD(0x5FC, 0x20C, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL)
191#define MX51_PAD_AUD3_BB_FS__GPIO_4_21 IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL) 227#define MX51_PAD_AUD3_BB_FS__GPIO_4_21 IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL)
228#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x600, 0x210, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL)
192#define MX51_PAD_CSPI1_MOSI__GPIO_4_22 IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL) 229#define MX51_PAD_CSPI1_MOSI__GPIO_4_22 IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL)
230#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x604, 0x214, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL)
193#define MX51_PAD_CSPI1_MISO__GPIO_4_23 IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL) 231#define MX51_PAD_CSPI1_MISO__GPIO_4_23 IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL)
232#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x608, 0x218, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL)
194#define MX51_PAD_CSPI1_SS0__GPIO_4_24 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL) 233#define MX51_PAD_CSPI1_SS0__GPIO_4_24 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL)
234#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 IOMUX_PAD(0x60C, 0x21C, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL)
195#define MX51_PAD_CSPI1_SS1__GPIO_4_25 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL) 235#define MX51_PAD_CSPI1_SS1__GPIO_4_25 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL)
236#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY IOMUX_PAD(0x610, 0x220, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL)
196#define MX51_PAD_CSPI1_RDY__GPIO_4_26 IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL) 237#define MX51_PAD_CSPI1_RDY__GPIO_4_26 IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL)
238#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x614, 0x224, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL)
197#define MX51_PAD_CSPI1_SCLK__GPIO_4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL) 239#define MX51_PAD_CSPI1_SCLK__GPIO_4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL)
198#define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) 240#define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
199#define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61C, 0x22C, 0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) 241#define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61C, 0x22C, 0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
@@ -236,14 +278,14 @@ typedef enum iomux_config {
236#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) 278#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, 0, 0x0, 0, MX51_USBH1_PAD_CTRL)
237#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) 279#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, 0, 0x0, 0, MX51_USBH1_PAD_CTRL)
238#define MX51_PAD_DI1_PIN11__GPIO_3_0 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL) 280#define MX51_PAD_DI1_PIN11__GPIO_3_0 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL)
239#define MX51_PAD_DI1_PIN12__GPIO_3_1 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL) 281#define MX51_PAD_DI1_PIN12__GPIO_3_1 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x978, 1, NO_PAD_CTRL)
240#define MX51_PAD_DI1_PIN13__GPIO_3_2 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL) 282#define MX51_PAD_DI1_PIN13__GPIO_3_2 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x97c, 1, NO_PAD_CTRL)
241#define MX51_PAD_DI1_D0_CS__GPIO_3_3 IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0, 0, NO_PAD_CTRL) 283#define MX51_PAD_DI1_D0_CS__GPIO_3_3 IOMUX_PAD(0x6B4, 0x2B4, 4, 0x980, 1, NO_PAD_CTRL)
242#define MX51_PAD_DI1_D1_CS__GPIO_3_4 IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0, 0, NO_PAD_CTRL) 284#define MX51_PAD_DI1_D1_CS__GPIO_3_4 IOMUX_PAD(0x6B8, 0x2B8, 4, 0x984, 1, NO_PAD_CTRL)
243#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5 IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0, 0, NO_PAD_CTRL) 285#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5 IOMUX_PAD(0x6BC, 0x2BC, 4, 0x988, 1, NO_PAD_CTRL)
244#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6 IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0, 0, NO_PAD_CTRL) 286#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6 IOMUX_PAD(0x6C0, 0x2C0, 4, 0x98c, 1, NO_PAD_CTRL)
245#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7 IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0, 0, NO_PAD_CTRL) 287#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7 IOMUX_PAD(0x6C4, 0x2C4, 4, 0x990, 1, NO_PAD_CTRL)
246#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8 IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0, 0, NO_PAD_CTRL) 288#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8 IOMUX_PAD(0x6C8, 0x2C8, 4, 0x994, 1, NO_PAD_CTRL)
247#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL) 289#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL)
248#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL) 290#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL)
249#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL) 291#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL)
@@ -294,32 +336,50 @@ typedef enum iomux_config {
294#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL) 336#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL)
295#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL) 337#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL)
296#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL) 338#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL)
297#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL) 339#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, IOMUX_CONFIG_SION, 0x0, 0, \
298#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL) 340 MX51_SDHCI_PAD_CTRL)
299#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL) 341#define MX51_PAD_SD1_CMD__AUD5_RXFS IOMUX_PAD(0x79C, 0x394, 1, 0x8e0, 1, NO_PAD_CTRL)
300#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL) 342#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, IOMUX_CONFIG_SION, 0x0, 0, \
301#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL) 343 MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
302#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL) 344#define MX51_PAD_SD1_CLK__AUD5_RXC IOMUX_PAD(0x7A0, 0x398, 1, 0x8dc, 1, NO_PAD_CTRL)
303#define MX51_PAD_GPIO_1_0__GPIO_1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL) 345#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, IOMUX_CONFIG_SION, 0x0, 0, \
304#define MX51_PAD_GPIO_1_1__GPIO_1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL) 346 MX51_SDHCI_PAD_CTRL)
305#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL) 347#define MX51_PAD_SD1_DATA0__AUD5_TXD IOMUX_PAD(0x7A4, 0x39C, 1, 0x8d8, 2, NO_PAD_CTRL)
306#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0, 0, NO_PAD_CTRL) 348#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, IOMUX_CONFIG_SION, 0x0, 0, \
307#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0, 0, NO_PAD_CTRL) 349 MX51_SDHCI_PAD_CTRL)
308#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0, 0, NO_PAD_CTRL) 350#define MX51_PAD_SD1_DATA1__AUD5_RXD IOMUX_PAD(0x7A8, 0x3A0, 1, 0x8d4, 2, NO_PAD_CTRL)
309#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0, 0, NO_PAD_CTRL) 351#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, IOMUX_CONFIG_SION, 0x0, 0, \
310#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0, 0, NO_PAD_CTRL) 352 MX51_SDHCI_PAD_CTRL)
311#define MX51_PAD_GPIO_1_2__GPIO_1_2 IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL) 353#define MX51_PAD_SD1_DATA2__AUD5_TXC IOMUX_PAD(0x7AC, 0x3A4, 1, 0x8e4, 2, NO_PAD_CTRL)
354#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, IOMUX_CONFIG_SION, 0x0, 0, \
355 MX51_SDHCI_PAD_CTRL)
356#define MX51_PAD_SD1_DATA3__AUD5_TXFS IOMUX_PAD(0x7B0, 0x3A8, 1, 0x8e8, 2, NO_PAD_CTRL)
357#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, IOMUX_CONFIG_SION, 0x0, 1, \
358 MX51_SDHCI_PAD_CTRL)
359#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, IOMUX_CONFIG_SION, 0x0, 0, \
360 MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
361#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, IOMUX_CONFIG_SION, 0x0, 0, \
362 MX51_SDHCI_PAD_CTRL)
363#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, IOMUX_CONFIG_SION, 0x0, 0, \
364 MX51_SDHCI_PAD_CTRL)
365#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, IOMUX_CONFIG_SION, 0x0, 0, \
366 MX51_SDHCI_PAD_CTRL)
367#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, IOMUX_CONFIG_SION, 0x0, 0, \
368 MX51_SDHCI_PAD_CTRL)
369#define MX51_PAD_GPIO_1_0__GPIO_1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
370#define MX51_PAD_GPIO_1_1__GPIO_1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
371#define MX51_PAD_GPIO_1_2__GPIO_1_2 IOMUX_PAD(0x7D4, 0x3CC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
312#define MX51_PAD_GPIO_1_2__I2C2_SCL IOMUX_PAD(0x7D4, 0x3CC, (2 | IOMUX_CONFIG_SION), \ 372#define MX51_PAD_GPIO_1_2__I2C2_SCL IOMUX_PAD(0x7D4, 0x3CC, (2 | IOMUX_CONFIG_SION), \
313 0x9b8, 3, MX51_I2C_PAD_CTRL) 373 0x9b8, 3, MX51_I2C_PAD_CTRL)
314#define MX51_PAD_GPIO_1_3__GPIO_1_3 IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL) 374#define MX51_PAD_GPIO_1_3__GPIO_1_3 IOMUX_PAD(0x7D8, 0x3D0, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
315#define MX51_PAD_GPIO_1_3__I2C2_SDA IOMUX_PAD(0x7D8, 0x3D0, (2 | IOMUX_CONFIG_SION), \ 375#define MX51_PAD_GPIO_1_3__I2C2_SDA IOMUX_PAD(0x7D8, 0x3D0, (2 | IOMUX_CONFIG_SION), \
316 0x9bc, 3, MX51_I2C_PAD_CTRL) 376 0x9bc, 3, MX51_I2C_PAD_CTRL)
317#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL) 377#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL)
318#define MX51_PAD_GPIO_1_4__GPIO_1_4 IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL) 378#define MX51_PAD_GPIO_1_4__GPIO_1_4 IOMUX_PAD(0x804, 0x3D8, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
319#define MX51_PAD_GPIO_1_5__GPIO_1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL) 379#define MX51_PAD_GPIO_1_5__GPIO_1_5 IOMUX_PAD(0x808, 0x3DC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
320#define MX51_PAD_GPIO_1_6__GPIO_1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) 380#define MX51_PAD_GPIO_1_6__GPIO_1_6 IOMUX_PAD(0x80C, 0x3E0, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
321#define MX51_PAD_GPIO_1_7__GPIO_1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) 381#define MX51_PAD_GPIO_1_7__GPIO_1_7 IOMUX_PAD(0x810, 0x3E4, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
322#define MX51_PAD_GPIO_1_8__GPIO_1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, MX51_GPIO_PAD_CTRL) 382#define MX51_PAD_GPIO_1_8__GPIO_1_8 IOMUX_PAD(0x814, 0x3E8, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
323#define MX51_PAD_GPIO_1_9__GPIO_1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL) 383#define MX51_PAD_GPIO_1_9__GPIO_1_9 IOMUX_PAD(0x818, 0x3EC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
324 384
325#endif /* __MACH_IOMUX_MX51_H__ */ 385#endif /* __MACH_IOMUX_MX51_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iram.h b/arch/arm/plat-mxc/include/mach/iram.h
new file mode 100644
index 000000000000..022690c33702
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iram.h
@@ -0,0 +1,41 @@
1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19#include <linux/errno.h>
20
21#ifdef CONFIG_IRAM_ALLOC
22
23int __init iram_init(unsigned long base, unsigned long size);
24void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr);
25void iram_free(unsigned long dma_addr, unsigned int size);
26
27#else
28
29static inline int __init iram_init(unsigned long base, unsigned long size)
30{
31 return -ENOMEM;
32}
33
34static inline void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr)
35{
36 return NULL;
37}
38
39static inline void iram_free(unsigned long base, unsigned long size) {}
40
41#endif
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h
index ed98b9c9f389..8bc59720b6e4 100644
--- a/arch/arm/plat-mxc/include/mach/mx21.h
+++ b/arch/arm/plat-mxc/include/mach/mx21.h
@@ -120,7 +120,7 @@
120#define MX21_INT_GPT1 26 120#define MX21_INT_GPT1 26
121#define MX21_INT_WDOG 27 121#define MX21_INT_WDOG 27
122#define MX21_INT_PCMCIA 28 122#define MX21_INT_PCMCIA 28
123#define MX21_INT_NANDFC 29 123#define MX21_INT_NFC 29
124#define MX21_INT_BMI 30 124#define MX21_INT_BMI 30
125#define MX21_INT_CSI 31 125#define MX21_INT_CSI 31
126#define MX21_INT_DMACH0 32 126#define MX21_INT_DMACH0 32
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index 4a6f800990f8..cf46a45b0d4e 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -50,8 +50,11 @@
50#define MX25_SSI1_BASE_ADDR 0x50034000 50#define MX25_SSI1_BASE_ADDR 0x50034000
51#define MX25_NFC_BASE_ADDR 0xbb000000 51#define MX25_NFC_BASE_ADDR 0xbb000000
52#define MX25_DRYICE_BASE_ADDR 0x53ffc000 52#define MX25_DRYICE_BASE_ADDR 0x53ffc000
53#define MX25_ESDHC1_BASE_ADDR 0x53fb4000
54#define MX25_ESDHC2_BASE_ADDR 0x53fb8000
53#define MX25_LCDC_BASE_ADDR 0x53fbc000 55#define MX25_LCDC_BASE_ADDR 0x53fbc000
54#define MX25_KPP_BASE_ADDR 0x43fa8000 56#define MX25_KPP_BASE_ADDR 0x43fa8000
57#define MX25_SDMA_BASE_ADDR 0x53fd4000
55#define MX25_OTG_BASE_ADDR 0x53ff4000 58#define MX25_OTG_BASE_ADDR 0x53ff4000
56#define MX25_CSI_BASE_ADDR 0x53ff8000 59#define MX25_CSI_BASE_ADDR 0x53ff8000
57 60
@@ -59,6 +62,8 @@
59#define MX25_INT_I2C1 3 62#define MX25_INT_I2C1 3
60#define MX25_INT_I2C2 4 63#define MX25_INT_I2C2 4
61#define MX25_INT_UART4 5 64#define MX25_INT_UART4 5
65#define MX25_INT_ESDHC2 8
66#define MX25_INT_ESDHC1 9
62#define MX25_INT_I2C3 10 67#define MX25_INT_I2C3 10
63#define MX25_INT_SSI2 11 68#define MX25_INT_SSI2 11
64#define MX25_INT_SSI1 12 69#define MX25_INT_SSI1 12
@@ -69,7 +74,8 @@
69#define MX25_INT_KPP 24 74#define MX25_INT_KPP 24
70#define MX25_INT_DRYICE 25 75#define MX25_INT_DRYICE 25
71#define MX25_INT_UART2 32 76#define MX25_INT_UART2 32
72#define MX25_INT_NANDFC 33 77#define MX25_INT_NFC 33
78#define MX25_INT_SDMA 34
73#define MX25_INT_LCDC 39 79#define MX25_INT_LCDC 39
74#define MX25_INT_UART5 40 80#define MX25_INT_UART5 40
75#define MX25_INT_CAN1 43 81#define MX25_INT_CAN1 43
@@ -77,4 +83,13 @@
77#define MX25_INT_UART1 45 83#define MX25_INT_UART1 45
78#define MX25_INT_FEC 57 84#define MX25_INT_FEC 57
79 85
86#define MX25_DMA_REQ_SSI2_RX1 22
87#define MX25_DMA_REQ_SSI2_TX1 23
88#define MX25_DMA_REQ_SSI2_RX0 24
89#define MX25_DMA_REQ_SSI2_TX0 25
90#define MX25_DMA_REQ_SSI1_RX1 26
91#define MX25_DMA_REQ_SSI1_TX1 27
92#define MX25_DMA_REQ_SSI1_RX0 28
93#define MX25_DMA_REQ_SSI1_TX0 29
94
80#endif /* ifndef __MACH_MX25_H__ */ 95#endif /* ifndef __MACH_MX25_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index a8ab2e02a8ca..2237ba2e5351 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -167,7 +167,7 @@ static inline void mx27_setup_weimcs(size_t cs,
167#define MX27_INT_GPT1 26 167#define MX27_INT_GPT1 26
168#define MX27_INT_WDOG 27 168#define MX27_INT_WDOG 27
169#define MX27_INT_PCMCIA 28 169#define MX27_INT_PCMCIA 28
170#define MX27_INT_NANDFC 29 170#define MX27_INT_NFC 29
171#define MX27_INT_ATA 30 171#define MX27_INT_ATA 30
172#define MX27_INT_CSI 31 172#define MX27_INT_CSI 31
173#define MX27_INT_DMACH0 32 173#define MX27_INT_DMACH0 32
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index afee3ab9d62e..03e2afabc9fc 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -168,7 +168,7 @@ static inline void mx31_setup_weimcs(size_t cs,
168#define MX31_INT_POWER_FAIL 30 168#define MX31_INT_POWER_FAIL 30
169#define MX31_INT_CCM_DVFS 31 169#define MX31_INT_CCM_DVFS 31
170#define MX31_INT_UART2 32 170#define MX31_INT_UART2 32
171#define MX31_INT_NANDFC 33 171#define MX31_INT_NFC 33
172#define MX31_INT_SDMA 34 172#define MX31_INT_SDMA 34
173#define MX31_INT_USB1 35 173#define MX31_INT_USB1 35
174#define MX31_INT_USB2 36 174#define MX31_INT_USB2 36
@@ -197,6 +197,15 @@ static inline void mx31_setup_weimcs(size_t cs,
197#define MX31_INT_EXT_WDOG 62 197#define MX31_INT_EXT_WDOG 62
198#define MX31_INT_EXT_TV 63 198#define MX31_INT_EXT_TV 63
199 199
200#define MX31_DMA_REQ_SSI2_RX1 22
201#define MX31_DMA_REQ_SSI2_TX1 23
202#define MX31_DMA_REQ_SSI2_RX0 24
203#define MX31_DMA_REQ_SSI2_TX0 25
204#define MX31_DMA_REQ_SSI1_RX1 26
205#define MX31_DMA_REQ_SSI1_TX1 27
206#define MX31_DMA_REQ_SSI1_RX0 28
207#define MX31_DMA_REQ_SSI1_TX0 29
208
200#define MX31_PROD_SIGNATURE 0x1 /* For MX31 */ 209#define MX31_PROD_SIGNATURE 0x1 /* For MX31 */
201 210
202/* silicon revisions specific to i.MX31 */ 211/* silicon revisions specific to i.MX31 */
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index af3038c12e39..ff905cb32458 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -1,5 +1,6 @@
1#ifndef __MACH_MX35_H__ 1#ifndef __MACH_MX35_H__
2#define __MACH_MX35_H__ 2#define __MACH_MX35_H__
3
3/* 4/*
4 * IRAM 5 * IRAM
5 */ 6 */
@@ -52,6 +53,9 @@
52#define MX35_GPIO3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xa4000) 53#define MX35_GPIO3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xa4000)
53#define MX35_SCC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xac000) 54#define MX35_SCC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xac000)
54#define MX35_RNGA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb0000) 55#define MX35_RNGA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb0000)
56#define MX35_ESDHC1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb4000)
57#define MX35_ESDHC2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb8000)
58#define MX35_ESDHC3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xbc000)
55#define MX35_IPU_CTRL_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc0000) 59#define MX35_IPU_CTRL_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc0000)
56#define MX35_AUDMUX_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc4000) 60#define MX35_AUDMUX_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc4000)
57#define MX35_GPIO1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xcc000) 61#define MX35_GPIO1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xcc000)
@@ -63,6 +67,8 @@
63#define MX35_CAN1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe4000) 67#define MX35_CAN1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe4000)
64#define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000) 68#define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000)
65#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000) 69#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000)
70#define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000)
71
66#define MX35_OTG_BASE_ADDR 0x53ff4000 72#define MX35_OTG_BASE_ADDR 0x53ff4000
67 73
68#define MX35_ROMP_BASE_ADDR 0x60000000 74#define MX35_ROMP_BASE_ADDR 0x60000000
@@ -122,9 +128,9 @@
122#define MX35_INT_I2C3 3 128#define MX35_INT_I2C3 3
123#define MX35_INT_I2C2 4 129#define MX35_INT_I2C2 4
124#define MX35_INT_RTIC 6 130#define MX35_INT_RTIC 6
125#define MX35_INT_MMC_SDHC1 7 131#define MX35_INT_ESDHC1 7
126#define MX35_INT_MMC_SDHC2 8 132#define MX35_INT_ESDHC2 8
127#define MX35_INT_MMC_SDHC3 9 133#define MX35_INT_ESDHC3 9
128#define MX35_INT_I2C1 10 134#define MX35_INT_I2C1 10
129#define MX35_INT_SSI1 11 135#define MX35_INT_SSI1 11
130#define MX35_INT_SSI2 12 136#define MX35_INT_SSI2 12
@@ -145,7 +151,7 @@
145#define MX35_INT_GPT 29 151#define MX35_INT_GPT 29
146#define MX35_INT_POWER_FAIL 30 152#define MX35_INT_POWER_FAIL 30
147#define MX35_INT_UART2 32 153#define MX35_INT_UART2 32
148#define MX35_INT_NANDFC 33 154#define MX35_INT_NFC 33
149#define MX35_INT_SDMA 34 155#define MX35_INT_SDMA 34
150#define MX35_INT_USBHS 35 156#define MX35_INT_USBHS 35
151#define MX35_INT_USBOTG 37 157#define MX35_INT_USBOTG 37
@@ -173,22 +179,18 @@
173#define MX35_INT_EXT_WDOG 62 179#define MX35_INT_EXT_WDOG 62
174#define MX35_INT_EXT_TV 63 180#define MX35_INT_EXT_TV 63
175 181
182#define MX35_DMA_REQ_SSI2_RX1 22
183#define MX35_DMA_REQ_SSI2_TX1 23
184#define MX35_DMA_REQ_SSI2_RX0 24
185#define MX35_DMA_REQ_SSI2_TX0 25
186#define MX35_DMA_REQ_SSI1_RX1 26
187#define MX35_DMA_REQ_SSI1_TX1 27
188#define MX35_DMA_REQ_SSI1_RX0 28
189#define MX35_DMA_REQ_SSI1_TX0 29
190
176#define MX35_PROD_SIGNATURE 0x1 /* For MX31 */ 191#define MX35_PROD_SIGNATURE 0x1 /* For MX31 */
177 192
178/* silicon revisions specific to i.MX31 */ 193#define MX35_SYSTEM_REV_MIN MX3x_CHIP_REV_1_0
179#define MX35_CHIP_REV_1_0 0x10
180#define MX35_CHIP_REV_1_1 0x11
181#define MX35_CHIP_REV_1_2 0x12
182#define MX35_CHIP_REV_1_3 0x13
183#define MX35_CHIP_REV_2_0 0x20
184#define MX35_CHIP_REV_2_1 0x21
185#define MX35_CHIP_REV_2_2 0x22
186#define MX35_CHIP_REV_2_3 0x23
187#define MX35_CHIP_REV_3_0 0x30
188#define MX35_CHIP_REV_3_1 0x31
189#define MX35_CHIP_REV_3_2 0x32
190
191#define MX35_SYSTEM_REV_MIN MX35_CHIP_REV_1_0
192#define MX35_SYSTEM_REV_NUM 3 194#define MX35_SYSTEM_REV_NUM 3
193 195
194#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS 196#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
index 7a356de385f5..d1bd26d7b8a6 100644
--- a/arch/arm/plat-mxc/include/mach/mx3x.h
+++ b/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -240,7 +240,7 @@
240 240
241#define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */ 241#define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */
242 242
243/* silicon revisions specific to i.MX31 */ 243/* silicon revisions specific to i.MX31 and i.MX35 */
244#define MX3x_CHIP_REV_1_0 0x10 244#define MX3x_CHIP_REV_1_0 0x10
245#define MX3x_CHIP_REV_1_1 0x11 245#define MX3x_CHIP_REV_1_1 0x11
246#define MX3x_CHIP_REV_1_2 0x12 246#define MX3x_CHIP_REV_1_2 0x12
@@ -267,6 +267,14 @@ static inline int mx31_revision(void)
267{ 267{
268 return mx31_cpu_rev; 268 return mx31_cpu_rev;
269} 269}
270
271extern unsigned int mx35_cpu_rev;
272extern void mx35_read_cpu_rev(void);
273
274static inline int mx35_revision(void)
275{
276 return mx35_cpu_rev;
277}
270#endif 278#endif
271 279
272#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS 280#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
@@ -389,19 +397,6 @@ static inline int mx31_revision(void)
389#define MXC_INT_EXT_WDOG MX3x_INT_EXT_WDOG 397#define MXC_INT_EXT_WDOG MX3x_INT_EXT_WDOG
390#define MXC_INT_EXT_TV MX3x_INT_EXT_TV 398#define MXC_INT_EXT_TV MX3x_INT_EXT_TV
391#define PROD_SIGNATURE MX3x_PROD_SIGNATURE 399#define PROD_SIGNATURE MX3x_PROD_SIGNATURE
392#define CHIP_REV_1_0 MX3x_CHIP_REV_1_0
393#define CHIP_REV_1_1 MX3x_CHIP_REV_1_1
394#define CHIP_REV_1_2 MX3x_CHIP_REV_1_2
395#define CHIP_REV_1_3 MX3x_CHIP_REV_1_3
396#define CHIP_REV_2_0 MX3x_CHIP_REV_2_0
397#define CHIP_REV_2_1 MX3x_CHIP_REV_2_1
398#define CHIP_REV_2_2 MX3x_CHIP_REV_2_2
399#define CHIP_REV_2_3 MX3x_CHIP_REV_2_3
400#define CHIP_REV_3_0 MX3x_CHIP_REV_3_0
401#define CHIP_REV_3_1 MX3x_CHIP_REV_3_1
402#define CHIP_REV_3_2 MX3x_CHIP_REV_3_2
403#define SYSTEM_REV_MIN MX3x_SYSTEM_REV_MIN
404#define SYSTEM_REV_NUM MX3x_SYSTEM_REV_NUM
405#endif 400#endif
406 401
407#endif /* ifndef __MACH_MX3x_H__ */ 402#endif /* ifndef __MACH_MX3x_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
index 5aad344d5651..2af7a1056fc1 100644
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -1,5 +1,5 @@
1#ifndef __ASM_ARCH_MXC_MX51_H__ 1#ifndef __MACH_MX51_H__
2#define __ASM_ARCH_MXC_MX51_H__ 2#define __MACH_MX51_H__
3 3
4/* 4/*
5 * MX51 memory map: 5 * MX51 memory map:
@@ -7,24 +7,23 @@
7 * 7 *
8 * Virt Phys Size What 8 * Virt Phys Size What
9 * --------------------------------------------------------------------------- 9 * ---------------------------------------------------------------------------
10 * FA3E0000 1FFE0000 128K IRAM (SCCv2 RAM) 10 * fa3e0000 1ffe0000 128K IRAM (SCCv2 RAM)
11 * 30000000 256M GPU 11 * 30000000 256M GPU
12 * 40000000 512M IPU 12 * 40000000 512M IPU
13 * FA200000 60000000 1M DEBUG 13 * fa200000 60000000 1M DEBUG
14 * FB100000 70000000 1M SPBA 0 14 * fb100000 70000000 1M SPBA 0
15 * FB000000 73F00000 1M AIPS 1 15 * fb000000 73f00000 1M AIPS 1
16 * FB200000 83F00000 1M AIPS 2 16 * fb200000 83f00000 1M AIPS 2
17 * 8FFFC000 16K TZIC (interrupt controller) 17 * 8fffc000 16K TZIC (interrupt controller)
18 * 90000000 256M CSD0 SDRAM/DDR 18 * 90000000 256M CSD0 SDRAM/DDR
19 * A0000000 256M CSD1 SDRAM/DDR 19 * a0000000 256M CSD1 SDRAM/DDR
20 * B0000000 128M CS0 Flash 20 * b0000000 128M CS0 Flash
21 * B8000000 128M CS1 Flash 21 * b8000000 128M CS1 Flash
22 * C0000000 128M CS2 Flash 22 * c0000000 128M CS2 Flash
23 * C8000000 64M CS3 Flash 23 * c8000000 64M CS3 Flash
24 * CC000000 32M CS4 SRAM 24 * cc000000 32M CS4 SRAM
25 * CE000000 32M CS5 SRAM 25 * ce000000 32M CS5 SRAM
26 * CFFF0000 64K NFC (NAND Flash AXI) 26 * cfff0000 64K NFC (NAND Flash AXI)
27 *
28 */ 27 */
29 28
30/* 29/*
@@ -36,65 +35,151 @@
36/* 35/*
37 * IRAM 36 * IRAM
38 */ 37 */
39#define MX51_IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ 38#define MX51_IRAM_BASE_ADDR 0x1ffe0000 /* internal ram */
40#define MX51_IRAM_BASE_ADDR_VIRT 0xFA3E0000 39#define MX51_IRAM_BASE_ADDR_VIRT 0xfa3e0000
41#define MX51_IRAM_PARTITIONS 16 40#define MX51_IRAM_PARTITIONS 16
42#define MX51_IRAM_PARTITIONS_TO1 12
43#define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */ 41#define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */
44 42
43#define MX51_GPU_BASE_ADDR 0x20000000
44#define MX51_GPU_CTRL_BASE_ADDR 0x30000000
45#define MX51_IPU_CTRL_BASE_ADDR 0x40000000
46
47#define MX51_DEBUG_BASE_ADDR 0x60000000
48#define MX51_DEBUG_BASE_ADDR_VIRT 0xfa200000
49#define MX51_DEBUG_SIZE SZ_1M
50
51#define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x01000)
52#define MX51_ETM_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x02000)
53#define MX51_TPIU_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x03000)
54#define MX51_CTI0_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x04000)
55#define MX51_CTI1_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x05000)
56#define MX51_CTI2_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x06000)
57#define MX51_CTI3_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x07000)
58#define MX51_CORTEX_DBG_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x08000)
59
45/* 60/*
46 * NFC 61 * SPBA global module enabled #0
47 */ 62 */
48#define MX51_NFC_AXI_BASE_ADDR 0xCFFF0000 /* NAND flash AXI */ 63#define MX51_SPBA0_BASE_ADDR 0x70000000
49#define MX51_NFC_AXI_SIZE SZ_64K 64#define MX51_SPBA0_BASE_ADDR_VIRT 0xfb100000
65#define MX51_SPBA0_SIZE SZ_1M
66
67#define MX51_ESDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000)
68#define MX51_ESDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x08000)
69#define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0c000)
70#define MX51_ECSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x10000)
71#define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x14000)
72#define MX51_ESDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x20000)
73#define MX51_ESDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x24000)
74#define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x28000)
75#define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x30000)
76#define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x34000)
77#define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x38000)
78#define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x3c000)
50 79
51/* 80/*
52 * Graphics Memory of GPU 81 * AIPS 1
53 */ 82 */
54#define MX51_GPU_BASE_ADDR 0x20000000 83#define MX51_AIPS1_BASE_ADDR 0x73f00000
55#define MX51_GPU2D_BASE_ADDR 0xD0000000 84#define MX51_AIPS1_BASE_ADDR_VIRT 0xfb000000
85#define MX51_AIPS1_SIZE SZ_1M
86
87#define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000)
88#define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x84000)
89#define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x88000)
90#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x8c000)
91#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x90000)
92#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x94000)
93#define MX51_WDOG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x98000)
94#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x9c000)
95#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa0000)
96#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa4000)
97#define MX51_IOMUXC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa8000)
98#define MX51_EPIT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xac000)
99#define MX51_EPIT2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb0000)
100#define MX51_PWM1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb4000)
101#define MX51_PWM2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb8000)
102#define MX51_UART1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xbc000)
103#define MX51_UART2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xc0000)
104#define MX51_SRC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd0000)
105#define MX51_CCM_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd4000)
106#define MX51_GPC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd8000)
56 107
57#define MX51_TZIC_BASE_ADDR_TO1 0x8FFFC000 108/*
58#define MX51_TZIC_BASE_ADDR 0xE0000000 109 * AIPS 2
110 */
111#define MX51_AIPS2_BASE_ADDR 0x83f00000
112#define MX51_AIPS2_BASE_ADDR_VIRT 0xfb200000
113#define MX51_AIPS2_SIZE SZ_1M
59 114
60#define MX51_DEBUG_BASE_ADDR 0x60000000 115#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x80000)
61#define MX51_DEBUG_BASE_ADDR_VIRT 0xFA200000 116#define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x84000)
62#define MX51_DEBUG_SIZE SZ_1M 117#define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x88000)
63#define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00001000) 118#define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x94000)
64#define MX51_ETM_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00002000) 119#define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x98000)
65#define MX51_TPIU_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00003000) 120#define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x9c000)
66#define MX51_CTI0_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00004000) 121#define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa0000)
67#define MX51_CTI1_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00005000) 122#define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa4000)
68#define MX51_CTI2_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00006000) 123#define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa8000)
69#define MX51_CTI3_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00007000) 124#define MX51_ECSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xac000)
70#define MX51_CORTEX_DBG_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00008000) 125#define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb0000)
126#define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb4000)
127#define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb8000)
128#define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xbc000)
129#define MX51_CSPI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc0000)
130#define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc4000)
131#define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc8000)
132#define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xcc000)
133#define MX51_AUDMUX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd0000)
134#define MX51_M4IF_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd8000)
135#define MX51_ESDCTL_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd9000)
136#define MX51_WEIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xda000)
137#define MX51_NFC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdb000)
138#define MX51_EMI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdbf00)
139#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdc000)
140#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe0000)
141#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe4000)
142#define MX51_SSI3BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe8000)
143#define MX51_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xec000)
144#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf0000)
145#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf4000)
146#define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf8000)
147
148#define MX51_CSD0_BASE_ADDR 0x90000000
149#define MX51_CSD1_BASE_ADDR 0xa0000000
150#define MX51_CS0_BASE_ADDR 0xb0000000
151#define MX51_CS1_BASE_ADDR 0xb8000000
152#define MX51_CS2_BASE_ADDR 0xc0000000
153#define MX51_CS3_BASE_ADDR 0xc8000000
154#define MX51_CS4_BASE_ADDR 0xcc000000
155#define MX51_CS5_BASE_ADDR 0xce000000
71 156
72/* 157/*
73 * SPBA global module enabled #0 158 * NFC
74 */ 159 */
75#define MX51_SPBA0_BASE_ADDR 0x70000000 160#define MX51_NFC_AXI_BASE_ADDR 0xcfff0000 /* NAND flash AXI */
76#define MX51_SPBA0_BASE_ADDR_VIRT 0xFB100000 161#define MX51_NFC_AXI_SIZE SZ_64K
77#define MX51_SPBA0_SIZE SZ_1M 162
163#define MX51_GPU2D_BASE_ADDR 0xd0000000
164#define MX51_TZIC_BASE_ADDR 0xe0000000
78 165
79#define MX51_MMC_SDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00004000) 166#define MX51_IO_ADDRESS(x) ( \
80#define MX51_MMC_SDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00008000) 167 IMX_IO_ADDRESS(x, MX51_IRAM) ?: \
81#define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0000C000) 168 IMX_IO_ADDRESS(x, MX51_DEBUG) ?: \
82#define MX51_CSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00010000) 169 IMX_IO_ADDRESS(x, MX51_SPBA0) ?: \
83#define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00014000) 170 IMX_IO_ADDRESS(x, MX51_AIPS1) ?: \
84#define MX51_MMC_SDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00020000) 171 IMX_IO_ADDRESS(x, MX51_AIPS2))
85#define MX51_MMC_SDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00024000) 172
86#define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00028000) 173/* This is currently used in <mach/debug-macro.S>, but should go away */
87#define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00030000) 174#define MX51_AIPS1_IO_ADDRESS(x) \
88#define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00034000) 175 (((x) - MX51_AIPS1_BASE_ADDR) + MX51_AIPS1_BASE_ADDR_VIRT)
89#define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00038000)
90#define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0003C000)
91 176
92/* 177/*
93 * defines for SPBA modules 178 * defines for SPBA modules
94 */ 179 */
95#define MX51_SPBA_SDHC1 0x04 180#define MX51_SPBA_SDHC1 0x04
96#define MX51_SPBA_SDHC2 0x08 181#define MX51_SPBA_SDHC2 0x08
97#define MX51_SPBA_UART3 0x0C 182#define MX51_SPBA_UART3 0x0c
98#define MX51_SPBA_CSPI1 0x10 183#define MX51_SPBA_CSPI1 0x10
99#define MX51_SPBA_SSI2 0x14 184#define MX51_SPBA_SSI2 0x14
100#define MX51_SPBA_SDHC3 0x20 185#define MX51_SPBA_SDHC3 0x20
@@ -103,35 +188,7 @@
103#define MX51_SPBA_ATA 0x30 188#define MX51_SPBA_ATA 0x30
104#define MX51_SPBA_SLIM 0x34 189#define MX51_SPBA_SLIM 0x34
105#define MX51_SPBA_HSI2C 0x38 190#define MX51_SPBA_HSI2C 0x38
106#define MX51_SPBA_CTRL 0x3C 191#define MX51_SPBA_CTRL 0x3c
107
108/*
109 * AIPS 1
110 */
111#define MX51_AIPS1_BASE_ADDR 0x73F00000
112#define MX51_AIPS1_BASE_ADDR_VIRT 0xFB000000
113#define MX51_AIPS1_SIZE SZ_1M
114
115#define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00080000)
116#define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00084000)
117#define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00088000)
118#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0008C000)
119#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00090000)
120#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00094000)
121#define MX51_WDOG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00098000)
122#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0009C000)
123#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A0000)
124#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A4000)
125#define MX51_IOMUXC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A8000)
126#define MX51_EPIT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000AC000)
127#define MX51_EPIT2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B0000)
128#define MX51_PWM1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B4000)
129#define MX51_PWM2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B8000)
130#define MX51_UART1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000BC000)
131#define MX51_UART2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000C0000)
132#define MX51_SRC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D0000)
133#define MX51_CCM_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D4000)
134#define MX51_GPC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D8000)
135 192
136/* 193/*
137 * Defines for modules using static and dynamic DMA channels 194 * Defines for modules using static and dynamic DMA channels
@@ -164,282 +221,186 @@
164#define MX51_MXC_DMA_CHANNEL_ATA_TX MXC_DMA_DYNAMIC_CHANNEL 221#define MX51_MXC_DMA_CHANNEL_ATA_TX MXC_DMA_DYNAMIC_CHANNEL
165#define MX51_MXC_DMA_CHANNEL_MEMORY MXC_DMA_DYNAMIC_CHANNEL 222#define MX51_MXC_DMA_CHANNEL_MEMORY MXC_DMA_DYNAMIC_CHANNEL
166 223
167/*
168 * AIPS 2
169 */
170#define MX51_AIPS2_BASE_ADDR 0x83F00000
171#define MX51_AIPS2_BASE_ADDR_VIRT 0xFB200000
172#define MX51_AIPS2_SIZE SZ_1M
173
174#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00080000)
175#define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00084000)
176#define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00088000)
177#define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00094000)
178#define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00098000)
179#define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x0009C000)
180#define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A0000)
181#define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A4000)
182#define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A8000)
183#define MX51_CSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000AC000)
184#define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B0000)
185#define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B4000)
186#define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B8000)
187#define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000BC000)
188#define MX51_CSPI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C0000)
189#define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C4000)
190#define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C8000)
191#define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000CC000)
192#define MX51_AUDMUX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D0000)
193#define MX51_M4IF_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D8000)
194#define MX51_ESDCTL_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D9000)
195#define MX51_WEIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DA000)
196#define MX51_NFC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DB000)
197#define MX51_EMI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DBF00)
198#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DC000)
199#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E0000)
200#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E4000)
201#define MX51_SSI3BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E8000)
202#define MX51_MXC_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000EC000)
203#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F0000)
204#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F4000)
205#define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F8000)
206
207/*
208 * Memory regions and CS
209 */
210#define MX51_GPU_CTRL_BASE_ADDR 0x30000000
211#define MX51_IPU_CTRL_BASE_ADDR 0x40000000
212#define MX51_CSD0_BASE_ADDR 0x90000000
213#define MX51_CSD1_BASE_ADDR 0xA0000000
214#define MX51_CS0_BASE_ADDR 0xB0000000
215#define MX51_CS1_BASE_ADDR 0xB8000000
216#define MX51_CS2_BASE_ADDR 0xC0000000
217#define MX51_CS3_BASE_ADDR 0xC8000000
218#define MX51_CS4_BASE_ADDR 0xCC000000
219#define MX51_CS5_BASE_ADDR 0xCE000000
220
221/* Does given address belongs to the specified memory region? */
222#define ADDRESS_IN_REGION(addr, start, size) \
223 (((addr) >= (start)) && ((addr) < (start)+(size)))
224
225/* Does given address belongs to the specified named `module'? */
226#define MX51_IS_MODULE(addr, module) \
227 ADDRESS_IN_REGION(addr, MX51_ ## module ## _BASE_ADDR, \
228 MX51_ ## module ## _SIZE)
229/*
230 * This macro defines the physical to virtual address mapping for all the
231 * peripheral modules. It is used by passing in the physical address as x
232 * and returning the virtual address. If the physical address is not mapped,
233 * it returns 0xDEADBEEF
234 */
235
236#define MX51_IO_ADDRESS(x) \
237 (void __iomem *) \
238 (MX51_IS_MODULE(x, IRAM) ? MX51_IRAM_IO_ADDRESS(x) : \
239 MX51_IS_MODULE(x, DEBUG) ? MX51_DEBUG_IO_ADDRESS(x) : \
240 MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) : \
241 MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) : \
242 MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) : \
243 0xDEADBEEF)
244
245/*
246 * define the address mapping macros: in physical address order
247 */
248#define MX51_IRAM_IO_ADDRESS(x) \
249 (((x) - MX51_IRAM_BASE_ADDR) + MX51_IRAM_BASE_ADDR_VIRT)
250
251#define MX51_DEBUG_IO_ADDRESS(x) \
252 (((x) - MX51_DEBUG_BASE_ADDR) + MX51_DEBUG_BASE_ADDR_VIRT)
253
254#define MX51_SPBA0_IO_ADDRESS(x) \
255 (((x) - MX51_SPBA0_BASE_ADDR) + MX51_SPBA0_BASE_ADDR_VIRT)
256
257#define MX51_AIPS1_IO_ADDRESS(x) \
258 (((x) - MX51_AIPS1_BASE_ADDR) + MX51_AIPS1_BASE_ADDR_VIRT)
259
260#define MX51_AIPS2_IO_ADDRESS(x) \
261 (((x) - MX51_AIPS2_BASE_ADDR) + MX51_AIPS2_BASE_ADDR_VIRT)
262
263#define MX51_IS_MEM_DEVICE_NONSHARED(x) 0 224#define MX51_IS_MEM_DEVICE_NONSHARED(x) 0
264 225
265/* 226/*
266 * DMA request assignments 227 * DMA request assignments
267 */ 228 */
268#define MX51_DMA_REQ_SSI3_TX1 47 229#define MX51_DMA_REQ_VPU 0
269#define MX51_DMA_REQ_SSI3_RX1 46 230#define MX51_DMA_REQ_GPC 1
270#define MX51_DMA_REQ_SPDIF 45 231#define MX51_DMA_REQ_ATA_RX 2
271#define MX51_DMA_REQ_UART3_TX 44 232#define MX51_DMA_REQ_ATA_TX 3
272#define MX51_DMA_REQ_UART3_RX 43 233#define MX51_DMA_REQ_ATA_TX_END 4
273#define MX51_DMA_REQ_SLIM_B_TX 42 234#define MX51_DMA_REQ_SLIM_B 5
274#define MX51_DMA_REQ_SDHC4 41 235#define MX51_DMA_REQ_CSPI1_RX 6
275#define MX51_DMA_REQ_SDHC3 40 236#define MX51_DMA_REQ_CSPI1_TX 7
276#define MX51_DMA_REQ_CSPI_TX 39 237#define MX51_DMA_REQ_CSPI2_RX 8
277#define MX51_DMA_REQ_CSPI_RX 38 238#define MX51_DMA_REQ_CSPI2_TX 9
278#define MX51_DMA_REQ_SSI3_TX2 37 239#define MX51_DMA_REQ_HS_I2C_TX 10
279#define MX51_DMA_REQ_IPU 36 240#define MX51_DMA_REQ_HS_I2C_RX 11
280#define MX51_DMA_REQ_SSI3_RX2 35 241#define MX51_DMA_REQ_FIRI_RX 12
281#define MX51_DMA_REQ_EPIT2 34 242#define MX51_DMA_REQ_FIRI_TX 13
282#define MX51_DMA_REQ_CTI2_1 33 243#define MX51_DMA_REQ_EXTREQ1 14
283#define MX51_DMA_REQ_EMI_WR 32 244#define MX51_DMA_REQ_GPU 15
284#define MX51_DMA_REQ_CTI2_0 31 245#define MX51_DMA_REQ_UART2_RX 16
285#define MX51_DMA_REQ_EMI_RD 30 246#define MX51_DMA_REQ_UART2_TX 17
286#define MX51_DMA_REQ_SSI1_TX1 29 247#define MX51_DMA_REQ_UART1_RX 18
287#define MX51_DMA_REQ_SSI1_RX1 28 248#define MX51_DMA_REQ_UART1_TX 19
288#define MX51_DMA_REQ_SSI1_TX2 27 249#define MX51_DMA_REQ_SDHC1 20
289#define MX51_DMA_REQ_SSI1_RX2 26 250#define MX51_DMA_REQ_SDHC2 21
290#define MX51_DMA_REQ_SSI2_TX1 25 251#define MX51_DMA_REQ_SSI2_RX1 22
291#define MX51_DMA_REQ_SSI2_RX1 24 252#define MX51_DMA_REQ_SSI2_TX1 23
292#define MX51_DMA_REQ_SSI2_TX2 23 253#define MX51_DMA_REQ_SSI2_RX0 24
293#define MX51_DMA_REQ_SSI2_RX2 22 254#define MX51_DMA_REQ_SSI2_TX0 25
294#define MX51_DMA_REQ_SDHC2 21 255#define MX51_DMA_REQ_SSI1_RX1 26
295#define MX51_DMA_REQ_SDHC1 20 256#define MX51_DMA_REQ_SSI1_TX1 27
296#define MX51_DMA_REQ_UART1_TX 19 257#define MX51_DMA_REQ_SSI1_RX0 28
297#define MX51_DMA_REQ_UART1_RX 18 258#define MX51_DMA_REQ_SSI1_TX0 29
298#define MX51_DMA_REQ_UART2_TX 17 259#define MX51_DMA_REQ_EMI_RD 30
299#define MX51_DMA_REQ_UART2_RX 16 260#define MX51_DMA_REQ_CTI2_0 31
300#define MX51_DMA_REQ_GPU 15 261#define MX51_DMA_REQ_EMI_WR 32
301#define MX51_DMA_REQ_EXTREQ1 14 262#define MX51_DMA_REQ_CTI2_1 33
302#define MX51_DMA_REQ_FIRI_TX 13 263#define MX51_DMA_REQ_EPIT2 34
303#define MX51_DMA_REQ_FIRI_RX 12 264#define MX51_DMA_REQ_SSI3_RX2 35
304#define MX51_DMA_REQ_HS_I2C_RX 11 265#define MX51_DMA_REQ_IPU 36
305#define MX51_DMA_REQ_HS_I2C_TX 10 266#define MX51_DMA_REQ_SSI3_TX2 37
306#define MX51_DMA_REQ_CSPI2_TX 9 267#define MX51_DMA_REQ_CSPI_RX 38
307#define MX51_DMA_REQ_CSPI2_RX 8 268#define MX51_DMA_REQ_CSPI_TX 39
308#define MX51_DMA_REQ_CSPI1_TX 7 269#define MX51_DMA_REQ_SDHC3 40
309#define MX51_DMA_REQ_CSPI1_RX 6 270#define MX51_DMA_REQ_SDHC4 41
310#define MX51_DMA_REQ_SLIM_B 5 271#define MX51_DMA_REQ_SLIM_B_TX 42
311#define MX51_DMA_REQ_ATA_TX_END 4 272#define MX51_DMA_REQ_UART3_RX 43
312#define MX51_DMA_REQ_ATA_TX 3 273#define MX51_DMA_REQ_UART3_TX 44
313#define MX51_DMA_REQ_ATA_RX 2 274#define MX51_DMA_REQ_SPDIF 45
314#define MX51_DMA_REQ_GPC 1 275#define MX51_DMA_REQ_SSI3_RX1 46
315#define MX51_DMA_REQ_VPU 0 276#define MX51_DMA_REQ_SSI3_TX1 47
316 277
317/* 278/*
318 * Interrupt numbers 279 * Interrupt numbers
319 */ 280 */
320#define MX51_MXC_INT_BASE 0 281#define MX51_MXC_INT_BASE 0
321#define MX51_MXC_INT_RESV0 0 282#define MX51_MXC_INT_RESV0 0
322#define MX51_MXC_INT_MMC_SDHC1 1 283#define MX51_INT_ESDHC1 1
323#define MX51_MXC_INT_MMC_SDHC2 2 284#define MX51_INT_ESDHC2 2
324#define MX51_MXC_INT_MMC_SDHC3 3 285#define MX51_INT_ESDHC3 3
325#define MX51_MXC_INT_MMC_SDHC4 4 286#define MX51_INT_ESDHC4 4
326#define MX51_MXC_INT_RESV5 5 287#define MX51_MXC_INT_RESV5 5
327#define MX51_MXC_INT_SDMA 6 288#define MX51_INT_SDMA 6
328#define MX51_MXC_INT_IOMUX 7 289#define MX51_MXC_INT_IOMUX 7
329#define MX51_MXC_INT_NFC 8 290#define MX51_INT_NFC 8
330#define MX51_MXC_INT_VPU 9 291#define MX51_MXC_INT_VPU 9
331#define MX51_MXC_INT_IPU_ERR 10 292#define MX51_MXC_INT_IPU_ERR 10
332#define MX51_MXC_INT_IPU_SYN 11 293#define MX51_MXC_INT_IPU_SYN 11
333#define MX51_MXC_INT_GPU 12 294#define MX51_MXC_INT_GPU 12
334#define MX51_MXC_INT_RESV13 13 295#define MX51_MXC_INT_RESV13 13
335#define MX51_MXC_INT_USB_H1 14 296#define MX51_MXC_INT_USB_H1 14
336#define MX51_MXC_INT_EMI 15 297#define MX51_MXC_INT_EMI 15
337#define MX51_MXC_INT_USB_H2 16 298#define MX51_MXC_INT_USB_H2 16
338#define MX51_MXC_INT_USB_H3 17 299#define MX51_MXC_INT_USB_H3 17
339#define MX51_MXC_INT_USB_OTG 18 300#define MX51_MXC_INT_USB_OTG 18
340#define MX51_MXC_INT_SAHARA_H0 19 301#define MX51_MXC_INT_SAHARA_H0 19
341#define MX51_MXC_INT_SAHARA_H1 20 302#define MX51_MXC_INT_SAHARA_H1 20
342#define MX51_MXC_INT_SCC_SMN 21 303#define MX51_MXC_INT_SCC_SMN 21
343#define MX51_MXC_INT_SCC_STZ 22 304#define MX51_MXC_INT_SCC_STZ 22
344#define MX51_MXC_INT_SCC_SCM 23 305#define MX51_MXC_INT_SCC_SCM 23
345#define MX51_MXC_INT_SRTC_NTZ 24 306#define MX51_MXC_INT_SRTC_NTZ 24
346#define MX51_MXC_INT_SRTC_TZ 25 307#define MX51_MXC_INT_SRTC_TZ 25
347#define MX51_MXC_INT_RTIC 26 308#define MX51_MXC_INT_RTIC 26
348#define MX51_MXC_INT_CSU 27 309#define MX51_MXC_INT_CSU 27
349#define MX51_MXC_INT_SLIM_B 28 310#define MX51_MXC_INT_SLIM_B 28
350#define MX51_MXC_INT_SSI1 29 311#define MX51_INT_SSI1 29
351#define MX51_MXC_INT_SSI2 30 312#define MX51_INT_SSI2 30
352#define MX51_MXC_INT_UART1 31 313#define MX51_INT_UART1 31
353#define MX51_MXC_INT_UART2 32 314#define MX51_INT_UART2 32
354#define MX51_MXC_INT_UART3 33 315#define MX51_INT_UART3 33
355#define MX51_MXC_INT_RESV34 34 316#define MX51_MXC_INT_RESV34 34
356#define MX51_MXC_INT_RESV35 35 317#define MX51_MXC_INT_RESV35 35
357#define MX51_MXC_INT_CSPI1 36 318#define MX51_INT_ECSPI1 36
358#define MX51_MXC_INT_CSPI2 37 319#define MX51_INT_ECSPI2 37
359#define MX51_MXC_INT_CSPI 38 320#define MX51_INT_CSPI 38
360#define MX51_MXC_INT_GPT 39 321#define MX51_MXC_INT_GPT 39
361#define MX51_MXC_INT_EPIT1 40 322#define MX51_MXC_INT_EPIT1 40
362#define MX51_MXC_INT_EPIT2 41 323#define MX51_MXC_INT_EPIT2 41
363#define MX51_MXC_INT_GPIO1_INT7 42 324#define MX51_MXC_INT_GPIO1_INT7 42
364#define MX51_MXC_INT_GPIO1_INT6 43 325#define MX51_MXC_INT_GPIO1_INT6 43
365#define MX51_MXC_INT_GPIO1_INT5 44 326#define MX51_MXC_INT_GPIO1_INT5 44
366#define MX51_MXC_INT_GPIO1_INT4 45 327#define MX51_MXC_INT_GPIO1_INT4 45
367#define MX51_MXC_INT_GPIO1_INT3 46 328#define MX51_MXC_INT_GPIO1_INT3 46
368#define MX51_MXC_INT_GPIO1_INT2 47 329#define MX51_MXC_INT_GPIO1_INT2 47
369#define MX51_MXC_INT_GPIO1_INT1 48 330#define MX51_MXC_INT_GPIO1_INT1 48
370#define MX51_MXC_INT_GPIO1_INT0 49 331#define MX51_MXC_INT_GPIO1_INT0 49
371#define MX51_MXC_INT_GPIO1_LOW 50 332#define MX51_MXC_INT_GPIO1_LOW 50
372#define MX51_MXC_INT_GPIO1_HIGH 51 333#define MX51_MXC_INT_GPIO1_HIGH 51
373#define MX51_MXC_INT_GPIO2_LOW 52 334#define MX51_MXC_INT_GPIO2_LOW 52
374#define MX51_MXC_INT_GPIO2_HIGH 53 335#define MX51_MXC_INT_GPIO2_HIGH 53
375#define MX51_MXC_INT_GPIO3_LOW 54 336#define MX51_MXC_INT_GPIO3_LOW 54
376#define MX51_MXC_INT_GPIO3_HIGH 55 337#define MX51_MXC_INT_GPIO3_HIGH 55
377#define MX51_MXC_INT_GPIO4_LOW 56 338#define MX51_MXC_INT_GPIO4_LOW 56
378#define MX51_MXC_INT_GPIO4_HIGH 57 339#define MX51_MXC_INT_GPIO4_HIGH 57
379#define MX51_MXC_INT_WDOG1 58 340#define MX51_MXC_INT_WDOG1 58
380#define MX51_MXC_INT_WDOG2 59 341#define MX51_MXC_INT_WDOG2 59
381#define MX51_MXC_INT_KPP 60 342#define MX51_MXC_INT_KPP 60
382#define MX51_MXC_INT_PWM1 61 343#define MX51_MXC_INT_PWM1 61
383#define MX51_MXC_INT_I2C1 62 344#define MX51_INT_I2C1 62
384#define MX51_MXC_INT_I2C2 63 345#define MX51_INT_I2C2 63
385#define MX51_MXC_INT_HS_I2C 64 346#define MX51_MXC_INT_HS_I2C 64
386#define MX51_MXC_INT_RESV65 65 347#define MX51_MXC_INT_RESV65 65
387#define MX51_MXC_INT_RESV66 66 348#define MX51_MXC_INT_RESV66 66
388#define MX51_MXC_INT_SIM_IPB 67 349#define MX51_MXC_INT_SIM_IPB 67
389#define MX51_MXC_INT_SIM_DAT 68 350#define MX51_MXC_INT_SIM_DAT 68
390#define MX51_MXC_INT_IIM 69 351#define MX51_MXC_INT_IIM 69
391#define MX51_MXC_INT_ATA 70 352#define MX51_MXC_INT_ATA 70
392#define MX51_MXC_INT_CCM1 71 353#define MX51_MXC_INT_CCM1 71
393#define MX51_MXC_INT_CCM2 72 354#define MX51_MXC_INT_CCM2 72
394#define MX51_MXC_INT_GPC1 73 355#define MX51_MXC_INT_GPC1 73
395#define MX51_MXC_INT_GPC2 74 356#define MX51_MXC_INT_GPC2 74
396#define MX51_MXC_INT_SRC 75 357#define MX51_MXC_INT_SRC 75
397#define MX51_MXC_INT_NM 76 358#define MX51_MXC_INT_NM 76
398#define MX51_MXC_INT_PMU 77 359#define MX51_MXC_INT_PMU 77
399#define MX51_MXC_INT_CTI_IRQ 78 360#define MX51_MXC_INT_CTI_IRQ 78
400#define MX51_MXC_INT_CTI1_TG0 79 361#define MX51_MXC_INT_CTI1_TG0 79
401#define MX51_MXC_INT_CTI1_TG1 80 362#define MX51_MXC_INT_CTI1_TG1 80
402#define MX51_MXC_INT_MCG_ERR 81 363#define MX51_MXC_INT_MCG_ERR 81
403#define MX51_MXC_INT_MCG_TMR 82 364#define MX51_MXC_INT_MCG_TMR 82
404#define MX51_MXC_INT_MCG_FUNC 83 365#define MX51_MXC_INT_MCG_FUNC 83
405#define MX51_MXC_INT_GPU2_IRQ 84 366#define MX51_MXC_INT_GPU2_IRQ 84
406#define MX51_MXC_INT_GPU2_BUSY 85 367#define MX51_MXC_INT_GPU2_BUSY 85
407#define MX51_MXC_INT_RESV86 86 368#define MX51_MXC_INT_RESV86 86
408#define MX51_MXC_INT_FEC 87 369#define MX51_INT_FEC 87
409#define MX51_MXC_INT_OWIRE 88 370#define MX51_MXC_INT_OWIRE 88
410#define MX51_MXC_INT_CTI1_TG2 89 371#define MX51_MXC_INT_CTI1_TG2 89
411#define MX51_MXC_INT_SJC 90 372#define MX51_MXC_INT_SJC 90
412#define MX51_MXC_INT_SPDIF 91 373#define MX51_MXC_INT_SPDIF 91
413#define MX51_MXC_INT_TVE 92 374#define MX51_MXC_INT_TVE 92
414#define MX51_MXC_INT_FIRI 93 375#define MX51_MXC_INT_FIRI 93
415#define MX51_MXC_INT_PWM2 94 376#define MX51_MXC_INT_PWM2 94
416#define MX51_MXC_INT_SLIM_EXP 95 377#define MX51_MXC_INT_SLIM_EXP 95
417#define MX51_MXC_INT_SSI3 96 378#define MX51_MXC_INT_SSI3 96
418#define MX51_MXC_INT_EMI_BOOT 97 379#define MX51_MXC_INT_EMI_BOOT 97
419#define MX51_MXC_INT_CTI1_TG3 98 380#define MX51_MXC_INT_CTI1_TG3 98
420#define MX51_MXC_INT_SMC_RX 99 381#define MX51_MXC_INT_SMC_RX 99
421#define MX51_MXC_INT_VPU_IDLE 100 382#define MX51_MXC_INT_VPU_IDLE 100
422#define MX51_MXC_INT_EMI_NFC 101 383#define MX51_MXC_INT_EMI_NFC 101
423#define MX51_MXC_INT_GPU_IDLE 102 384#define MX51_MXC_INT_GPU_IDLE 102
424 385
425/* silicon revisions specific to i.MX51 */ 386/* silicon revisions specific to i.MX51 */
426#define MX51_CHIP_REV_1_0 0x10 387#define MX51_CHIP_REV_1_0 0x10
427#define MX51_CHIP_REV_1_1 0x11 388#define MX51_CHIP_REV_1_1 0x11
428#define MX51_CHIP_REV_1_2 0x12 389#define MX51_CHIP_REV_1_2 0x12
429#define MX51_CHIP_REV_1_3 0x13 390#define MX51_CHIP_REV_1_3 0x13
430#define MX51_CHIP_REV_2_0 0x20 391#define MX51_CHIP_REV_2_0 0x20
431#define MX51_CHIP_REV_2_1 0x21 392#define MX51_CHIP_REV_2_1 0x21
432#define MX51_CHIP_REV_2_2 0x22 393#define MX51_CHIP_REV_2_2 0x22
433#define MX51_CHIP_REV_2_3 0x23 394#define MX51_CHIP_REV_2_3 0x23
434#define MX51_CHIP_REV_3_0 0x30 395#define MX51_CHIP_REV_3_0 0x30
435#define MX51_CHIP_REV_3_1 0x31 396#define MX51_CHIP_REV_3_1 0x31
436#define MX51_CHIP_REV_3_2 0x32 397#define MX51_CHIP_REV_3_2 0x32
437
438/* Mandatory defines used globally */
439 398
440#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) 399#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
441
442extern int mx51_revision(void); 400extern int mx51_revision(void);
443#endif 401#endif
444 402
445#endif /* __ASM_ARCH_MXC_MX51_H__ */ 403/* tape-out 1 defines */
404#define MX51_TZIC_BASE_ADDR_TO1 0x8fffc000
405
406#endif /* ifndef __MACH_MX51_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
index 4acd1143a9bd..95be51bfe9a9 100644
--- a/arch/arm/plat-mxc/include/mach/system.h
+++ b/arch/arm/plat-mxc/include/mach/system.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright (C) 1999 ARM Limited 2 * Copyright (C) 1999 ARM Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd 3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 4 * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
@@ -28,8 +28,34 @@ static inline void arch_idle(void)
28 mxc91231_prepare_idle(); 28 mxc91231_prepare_idle();
29 } 29 }
30#endif 30#endif
31 31 /* fix i.MX31 errata TLSbo65953 and i.MX35 errata ENGcm09472 */
32 cpu_do_idle(); 32 if (cpu_is_mx31() || cpu_is_mx35()) {
33 unsigned long reg = 0;
34 __asm__ __volatile__(
35 /* disable I and D cache */
36 "mrc p15, 0, %0, c1, c0, 0\n"
37 "bic %0, %0, #0x00001000\n"
38 "bic %0, %0, #0x00000004\n"
39 "mcr p15, 0, %0, c1, c0, 0\n"
40 /* invalidate I cache */
41 "mov %0, #0\n"
42 "mcr p15, 0, %0, c7, c5, 0\n"
43 /* clear and invalidate D cache */
44 "mov %0, #0\n"
45 "mcr p15, 0, %0, c7, c14, 0\n"
46 /* WFI */
47 "mov %0, #0\n"
48 "mcr p15, 0, %0, c7, c0, 4\n"
49 "nop\n" "nop\n" "nop\n" "nop\n"
50 "nop\n" "nop\n" "nop\n"
51 /* enable I and D cache */
52 "mrc p15, 0, %0, c1, c0, 0\n"
53 "orr %0, %0, #0x00001000\n"
54 "orr %0, %0, #0x00000004\n"
55 "mcr p15, 0, %0, c1, c0, 0\n"
56 : "=r" (reg));
57 } else
58 cpu_do_idle();
33} 59}
34 60
35void arch_reset(char mode, const char *cmd); 61void arch_reset(char mode, const char *cmd);
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index d9bd37e4667a..9dd9c2085aad 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -99,6 +99,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
99 uart_base = MX3X_UART2_BASE_ADDR; 99 uart_base = MX3X_UART2_BASE_ADDR;
100 break; 100 break;
101 case MACH_TYPE_MX51_BABBAGE: 101 case MACH_TYPE_MX51_BABBAGE:
102 case MACH_TYPE_EUKREA_CPUIMX51SD:
102 uart_base = MX51_UART1_BASE_ADDR; 103 uart_base = MX51_UART1_BASE_ADDR;
103 break; 104 break;
104 default: 105 default:
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-01 17:08:27 -0500