diff options
| author | Yong Shen <yong.shen@freescale.com> | 2011-01-06 23:25:34 -0500 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2011-01-07 09:20:53 -0500 |
| commit | 410d3458e56bfe85ea4ac6358d5ae16d2f9acda6 (patch) | |
| tree | 7b1c82cdaf1c6f2f435bbf3d0a69273f2d665c0c /arch/arm/plat-mxc/include/mach | |
| parent | 0d7671ee66964760a718aa6d0277453b02a2c9b3 (diff) | |
ARM i.MX53 enable sdhc support on EVK board
1. changes some register address to fit macro definition
2. add platform data and clock for sdhc
Signed-off-by: Yong Shen <yong.shen@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/plat-mxc/include/mach')
| -rw-r--r-- | arch/arm/plat-mxc/include/mach/mx53.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h index a35e0c79bf23..340937f94e6f 100644 --- a/arch/arm/plat-mxc/include/mach/mx53.h +++ b/arch/arm/plat-mxc/include/mach/mx53.h | |||
| @@ -53,13 +53,13 @@ | |||
| 53 | #define MX53_SPBA0_BASE_ADDR 0x50000000 | 53 | #define MX53_SPBA0_BASE_ADDR 0x50000000 |
| 54 | #define MX53_SPBA0_SIZE SZ_1M | 54 | #define MX53_SPBA0_SIZE SZ_1M |
| 55 | 55 | ||
| 56 | #define MX53_MMC_SDHC1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00004000) | 56 | #define MX53_ESDHC1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00004000) |
| 57 | #define MX53_MMC_SDHC2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00008000) | 57 | #define MX53_ESDHC2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00008000) |
| 58 | #define MX53_UART3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0000C000) | 58 | #define MX53_UART3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0000C000) |
| 59 | #define MX53_CSPI1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00010000) | 59 | #define MX53_CSPI1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00010000) |
| 60 | #define MX53_SSI2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00014000) | 60 | #define MX53_SSI2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00014000) |
| 61 | #define MX53_MMC_SDHC3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00020000) | 61 | #define MX53_ESDHC3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00020000) |
| 62 | #define MX53_MMC_SDHC4_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00024000) | 62 | #define MX53_ESDHC4_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00024000) |
| 63 | #define MX53_SPDIF_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00028000) | 63 | #define MX53_SPDIF_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00028000) |
| 64 | #define MX53_ASRC_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0002C000) | 64 | #define MX53_ASRC_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0002C000) |
| 65 | #define MX53_ATA_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00030000) | 65 | #define MX53_ATA_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00030000) |
| @@ -229,10 +229,10 @@ | |||
| 229 | * Interrupt numbers | 229 | * Interrupt numbers |
| 230 | */ | 230 | */ |
| 231 | #define MX53_INT_RESV0 0 | 231 | #define MX53_INT_RESV0 0 |
| 232 | #define MX53_INT_MMC_SDHC1 1 | 232 | #define MX53_INT_ESDHC1 1 |
| 233 | #define MX53_INT_MMC_SDHC2 2 | 233 | #define MX53_INT_ESDHC2 2 |
| 234 | #define MX53_INT_MMC_SDHC3 3 | 234 | #define MX53_INT_ESDHC3 3 |
| 235 | #define MX53_INT_MMC_SDHC4 4 | 235 | #define MX53_INT_ESDHC4 4 |
| 236 | #define MX53_INT_RESV5 5 | 236 | #define MX53_INT_RESV5 5 |
| 237 | #define MX53_INT_SDMA 6 | 237 | #define MX53_INT_SDMA 6 |
| 238 | #define MX53_INT_IOMUX 7 | 238 | #define MX53_INT_IOMUX 7 |