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authorUwe Kleine-König <u.kleine-koenig@pengutronix.de>2010-06-16 13:25:34 -0400
committerUwe Kleine-König <u.kleine-koenig@pengutronix.de>2010-06-30 03:00:44 -0400
commit7cdc8fa7120f97f40d36547854ae127dc0318e3a (patch)
tree54d2b57a0f0f14063fa995b99c7a64de9d473dc1 /arch/arm/plat-mxc/include/mach/mx35.h
parent4a9b8b0b061ef750b5ef31d1e9d2fa0206731f2f (diff)
ARM: imx: dynamically register imx-i2c devices (imx35)
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Diffstat (limited to 'arch/arm/plat-mxc/include/mach/mx35.h')
-rw-r--r--arch/arm/plat-mxc/include/mach/mx35.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index 526a55842ae5..cda60c715127 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -18,7 +18,7 @@
18#define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000) 18#define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000)
19#define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000) 19#define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000)
20#define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000) 20#define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000)
21#define MX35_I2C_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000) 21#define MX35_I2C1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000)
22#define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000) 22#define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000)
23#define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000) 23#define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000)
24#define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000) 24#define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000)
@@ -123,7 +123,7 @@
123#define MX35_INT_MMC_SDHC1 7 123#define MX35_INT_MMC_SDHC1 7
124#define MX35_INT_MMC_SDHC2 8 124#define MX35_INT_MMC_SDHC2 8
125#define MX35_INT_MMC_SDHC3 9 125#define MX35_INT_MMC_SDHC3 9
126#define MX35_INT_I2C 10 126#define MX35_INT_I2C1 10
127#define MX35_INT_SSI1 11 127#define MX35_INT_SSI1 11
128#define MX35_INT_SSI2 12 128#define MX35_INT_SSI2 12
129#define MX35_INT_CSPI2 13 129#define MX35_INT_CSPI2 13