diff options
author | Uwe Kleine-König <u.kleine-koenig@pengutronix.de> | 2010-01-07 05:27:17 -0500 |
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committer | Uwe Kleine-König <u.kleine-koenig@pengutronix.de> | 2010-01-08 10:45:24 -0500 |
commit | a8dfb6462a033984b99fee4122fe0799a31f5bb4 (patch) | |
tree | bc71dbed2b59a897d1f5f90b541fc7d0f6b4ae48 /arch/arm/plat-mxc/include/mach/mx31.h | |
parent | 3cdd54417d0f821825a353f7273d356399112f56 (diff) |
imx: define functions to configure chip selects in the WEIM
This has the addional effect that the macros CSCR_U, CSCR_L and CSCR_A
are not used anymore in mach-pcm038.c and mach-qong.c. These still use
the deprecated IO_ADDRESS macro and shouldn't be used in new code.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Holger Schurig <hs4233@mail.mn-solutions.de>
Cc: Dmitriy Taychenachev <dimichxp@gmail.com>
Diffstat (limited to 'arch/arm/plat-mxc/include/mach/mx31.h')
-rw-r--r-- | arch/arm/plat-mxc/include/mach/mx31.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index 62d26da10c66..fb90e119c2b5 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h | |||
@@ -1,6 +1,10 @@ | |||
1 | #ifndef __MACH_MX31_H__ | 1 | #ifndef __MACH_MX31_H__ |
2 | #define __MACH_MX31_H__ | 2 | #define __MACH_MX31_H__ |
3 | 3 | ||
4 | #ifndef __ASSEMBLER__ | ||
5 | #include <linux/io.h> | ||
6 | #endif | ||
7 | |||
4 | /* | 8 | /* |
5 | * IRAM | 9 | * IRAM |
6 | */ | 10 | */ |
@@ -110,6 +114,11 @@ | |||
110 | #define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000) | 114 | #define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000) |
111 | #define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR | 115 | #define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR |
112 | 116 | ||
117 | #define MX31_WEIM_CSCRx_BASE_ADDR(cs) (MX31_WEIM_BASE_ADDR + (cs) * 0x10) | ||
118 | #define MX31_WEIM_CSCRxU(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs)) | ||
119 | #define MX31_WEIM_CSCRxL(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x4) | ||
120 | #define MX31_WEIM_CSCRxA(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x8) | ||
121 | |||
113 | #define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000 | 122 | #define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000 |
114 | 123 | ||
115 | #define MX31_IO_ADDRESS(x) ( \ | 124 | #define MX31_IO_ADDRESS(x) ( \ |
@@ -119,6 +128,16 @@ | |||
119 | IMX_IO_ADDRESS(x, MX31_X_MEMC) ?: \ | 128 | IMX_IO_ADDRESS(x, MX31_X_MEMC) ?: \ |
120 | IMX_IO_ADDRESS(x, MX31_SPBA0)) | 129 | IMX_IO_ADDRESS(x, MX31_SPBA0)) |
121 | 130 | ||
131 | #ifndef __ASSEMBLER__ | ||
132 | static inline void mx31_setup_weimcs(size_t cs, | ||
133 | unsigned upper, unsigned lower, unsigned addional) | ||
134 | { | ||
135 | __raw_writel(upper, MX31_IO_ADDRESS(MX31_WEIM_CSCRxU(cs))); | ||
136 | __raw_writel(lower, MX31_IO_ADDRESS(MX31_WEIM_CSCRxL(cs))); | ||
137 | __raw_writel(addional, MX31_IO_ADDRESS(MX31_WEIM_CSCRxA(cs))); | ||
138 | } | ||
139 | #endif | ||
140 | |||
122 | #define MX31_INT_I2C3 3 | 141 | #define MX31_INT_I2C3 3 |
123 | #define MX31_INT_I2C2 4 | 142 | #define MX31_INT_I2C2 4 |
124 | #define MX31_INT_MPEG4_ENCODER 5 | 143 | #define MX31_INT_MPEG4_ENCODER 5 |