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authorUwe Kleine-König <u.kleine-koenig@pengutronix.de>2010-11-10 16:15:45 -0500
committerUwe Kleine-König <u.kleine-koenig@pengutronix.de>2010-11-17 04:01:38 -0500
commit5f3d1092a949b33d01c95b7f5e5a83672629f131 (patch)
tree538bea4efeec3c2900a1ca2205d8dca6ea9e3c7b /arch/arm/plat-mxc/include/mach/mx25.h
parent224b8c83641c2f31e3efc9bc5956636cc42cadf7 (diff)
ARM: mx25: dynamically allocate mxc_pwm devices
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Diffstat (limited to 'arch/arm/plat-mxc/include/mach/mx25.h')
-rw-r--r--arch/arm/plat-mxc/include/mach/mx25.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index 0d31f828d218..cea851f09ca7 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -19,10 +19,14 @@
19#define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) 19#define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000)
20#define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000) 20#define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000)
21#define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000) 21#define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000)
22#define MX25_PWM2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa0000)
22#define MX25_GPIO3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa4000) 23#define MX25_GPIO3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa4000)
24#define MX25_PWM3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa8000)
25#define MX25_PWM4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xc8000)
23#define MX25_GPIO1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xcc000) 26#define MX25_GPIO1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xcc000)
24#define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000) 27#define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000)
25#define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000) 28#define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000)
29#define MX25_PWM1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xe0000)
26 30
27#define MX25_UART1_BASE_ADDR 0x43f90000 31#define MX25_UART1_BASE_ADDR 0x43f90000
28#define MX25_UART2_BASE_ADDR 0x43f94000 32#define MX25_UART2_BASE_ADDR 0x43f94000
@@ -66,13 +70,17 @@
66#define MX25_INT_UART3 18 70#define MX25_INT_UART3 18
67#define MX25_INT_KPP 24 71#define MX25_INT_KPP 24
68#define MX25_INT_DRYICE 25 72#define MX25_INT_DRYICE 25
73#define MX25_INT_PWM1 26
69#define MX25_INT_UART2 32 74#define MX25_INT_UART2 32
70#define MX25_INT_NFC 33 75#define MX25_INT_NFC 33
71#define MX25_INT_SDMA 34 76#define MX25_INT_SDMA 34
72#define MX25_INT_USB_HS 35 77#define MX25_INT_USB_HS 35
78#define MX25_INT_PWM2 36
73#define MX25_INT_USB_OTG 37 79#define MX25_INT_USB_OTG 37
74#define MX25_INT_LCDC 39 80#define MX25_INT_LCDC 39
75#define MX25_INT_UART5 40 81#define MX25_INT_UART5 40
82#define MX25_INT_PWM3 41
83#define MX25_INT_PWM4 42
76#define MX25_INT_CAN1 43 84#define MX25_INT_CAN1 43
77#define MX25_INT_CAN2 44 85#define MX25_INT_CAN2 44
78#define MX25_INT_UART1 45 86#define MX25_INT_UART1 45