diff options
author | Uwe Kleine-König <u.kleine-koenig@pengutronix.de> | 2010-11-11 04:52:33 -0500 |
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committer | Uwe Kleine-König <u.kleine-koenig@pengutronix.de> | 2010-11-17 04:01:38 -0500 |
commit | d485c7e71675abdd6133128e596b41284c2ee7b5 (patch) | |
tree | afa70c3ace0be126f27db3ef0a08d51d07a8fbb8 /arch/arm/plat-mxc/include/mach/mx21.h | |
parent | 5f3d1092a949b33d01c95b7f5e5a83672629f131 (diff) |
ARM: mx25: move registration of gpios to plat-mxc/gpio.c
To use common macros to define the gpio ports for imx{1,21,25,27} the
existing ones had to made more general and a few more base address defines
were necessary.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Diffstat (limited to 'arch/arm/plat-mxc/include/mach/mx21.h')
-rw-r--r-- | arch/arm/plat-mxc/include/mach/mx21.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h index a82f59063318..6cd049ebbd8d 100644 --- a/arch/arm/plat-mxc/include/mach/mx21.h +++ b/arch/arm/plat-mxc/include/mach/mx21.h | |||
@@ -48,6 +48,12 @@ | |||
48 | #define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000) | 48 | #define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000) |
49 | #define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000) | 49 | #define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000) |
50 | #define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000) | 50 | #define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000) |
51 | #define MX21_GPIO1_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x000) | ||
52 | #define MX21_GPIO2_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x100) | ||
53 | #define MX21_GPIO3_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x200) | ||
54 | #define MX21_GPIO4_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x300) | ||
55 | #define MX21_GPIO5_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x400) | ||
56 | #define MX21_GPIO6_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x500) | ||
51 | #define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000) | 57 | #define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000) |
52 | #define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000) | 58 | #define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000) |
53 | #define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000) | 59 | #define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000) |