mx5: Add registration of GPIOs for MX5 devices

Register the gpio irqs on Freescale's MX51 Babbage HW.

Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com>
Signed-off-by: Amit Kucheria <amit.kucheria@canonical.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

1 files changed, 2 insertions, 3 deletions

diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index 70b23893f094..71437c61cfd7 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -3,7 +3,7 @@
  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
  *
  * Based on code from Freescale,
- * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -38,7 +38,6 @@ static int gpio_table_size;
 #define GPIO_ICR2       (cpu_is_mx1_mx2() ? 0x2C : 0x10)
 #define GPIO_IMR        (cpu_is_mx1_mx2() ? 0x30 : 0x14)
 #define GPIO_ISR        (cpu_is_mx1_mx2() ? 0x34 : 0x18)
-#define GPIO_ISR        (cpu_is_mx1_mx2() ? 0x34 : 0x18)
 
 #define GPIO_INT_LOW_LEV        (cpu_is_mx1_mx2() ? 0x3 : 0x0)
 #define GPIO_INT_HIGH_LEV       (cpu_is_mx1_mx2() ? 0x2 : 0x1)
@@ -289,7 +288,7 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
                 /* its a serious configuration bug when it fails */
                 BUG_ON( gpiochip_add(&port[i].chip) < 0 );
 
-                if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25()) {
+                if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51()) {
                         /* setup one handler for each entry */
                         set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
                         set_irq_data(port[i].irq, &port[i]);