diff options
author | Sascha Hauer <s.hauer@pengutronix.de> | 2010-02-04 08:45:11 -0500 |
---|---|---|
committer | Sascha Hauer <s.hauer@pengutronix.de> | 2010-02-04 09:56:34 -0500 |
commit | 84ab80616b0eb5fac4d1970f10ea1b3cf75280e1 (patch) | |
tree | 5b58e17cffeb5f9966e0efe3d47e589fecafa7eb /arch/arm/plat-mxc/ehci.c | |
parent | ba593e5966440deec8684863e0cba9b502c4a377 (diff) |
i.MX ehci platform support: Some fixes
- The SIC mask is only 2bits wide, not 4
- MX31_OTG_PM_BIT and MX31_H1_PM_BIT use negative logic
- clear MX31_H1_DT_BIT and MX31_H2_DT_BIT so that they can be cleared,
not only set.
- return -EINVAL if called with an invalid controller number
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Daniel Mack <daniel@caiaq.de>
Diffstat (limited to 'arch/arm/plat-mxc/ehci.c')
-rw-r--r-- | arch/arm/plat-mxc/ehci.c | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c index 8df03f36295c..586b55dc2ab1 100644 --- a/arch/arm/plat-mxc/ehci.c +++ b/arch/arm/plat-mxc/ehci.c | |||
@@ -25,16 +25,16 @@ | |||
25 | #define USBCTRL_OTGBASE_OFFSET 0x600 | 25 | #define USBCTRL_OTGBASE_OFFSET 0x600 |
26 | 26 | ||
27 | #define MX31_OTG_SIC_SHIFT 29 | 27 | #define MX31_OTG_SIC_SHIFT 29 |
28 | #define MX31_OTG_SIC_MASK (0xf << MX31_OTG_SIC_SHIFT) | 28 | #define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT) |
29 | #define MX31_OTG_PM_BIT (1 << 24) | 29 | #define MX31_OTG_PM_BIT (1 << 24) |
30 | 30 | ||
31 | #define MX31_H2_SIC_SHIFT 21 | 31 | #define MX31_H2_SIC_SHIFT 21 |
32 | #define MX31_H2_SIC_MASK (0xf << MX31_H2_SIC_SHIFT) | 32 | #define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT) |
33 | #define MX31_H2_PM_BIT (1 << 16) | 33 | #define MX31_H2_PM_BIT (1 << 16) |
34 | #define MX31_H2_DT_BIT (1 << 5) | 34 | #define MX31_H2_DT_BIT (1 << 5) |
35 | 35 | ||
36 | #define MX31_H1_SIC_SHIFT 13 | 36 | #define MX31_H1_SIC_SHIFT 13 |
37 | #define MX31_H1_SIC_MASK (0xf << MX31_H1_SIC_SHIFT) | 37 | #define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT) |
38 | #define MX31_H1_PM_BIT (1 << 8) | 38 | #define MX31_H1_PM_BIT (1 << 8) |
39 | #define MX31_H1_DT_BIT (1 << 4) | 39 | #define MX31_H1_DT_BIT (1 << 4) |
40 | 40 | ||
@@ -51,15 +51,15 @@ int mxc_set_usbcontrol(int port, unsigned int flags) | |||
51 | v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); | 51 | v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); |
52 | v |= (flags & MXC_EHCI_INTERFACE_MASK) | 52 | v |= (flags & MXC_EHCI_INTERFACE_MASK) |
53 | << MX31_OTG_SIC_SHIFT; | 53 | << MX31_OTG_SIC_SHIFT; |
54 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) | 54 | if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) |
55 | v |= MX31_OTG_PM_BIT; | 55 | v |= MX31_OTG_PM_BIT; |
56 | 56 | ||
57 | break; | 57 | break; |
58 | case 1: /* H1 port */ | 58 | case 1: /* H1 port */ |
59 | v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT); | 59 | v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT); |
60 | v |= (flags & MXC_EHCI_INTERFACE_MASK) | 60 | v |= (flags & MXC_EHCI_INTERFACE_MASK) |
61 | << MX31_H1_SIC_SHIFT; | 61 | << MX31_H1_SIC_SHIFT; |
62 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) | 62 | if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) |
63 | v |= MX31_H1_PM_BIT; | 63 | v |= MX31_H1_PM_BIT; |
64 | 64 | ||
65 | if (!(flags & MXC_EHCI_TTL_ENABLED)) | 65 | if (!(flags & MXC_EHCI_TTL_ENABLED)) |
@@ -67,7 +67,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags) | |||
67 | 67 | ||
68 | break; | 68 | break; |
69 | case 2: /* H2 port */ | 69 | case 2: /* H2 port */ |
70 | v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT); | 70 | v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT); |
71 | v |= (flags & MXC_EHCI_INTERFACE_MASK) | 71 | v |= (flags & MXC_EHCI_INTERFACE_MASK) |
72 | << MX31_H2_SIC_SHIFT; | 72 | << MX31_H2_SIC_SHIFT; |
73 | if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) | 73 | if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) |
@@ -77,6 +77,8 @@ int mxc_set_usbcontrol(int port, unsigned int flags) | |||
77 | v |= MX31_H2_DT_BIT; | 77 | v |= MX31_H2_DT_BIT; |
78 | 78 | ||
79 | break; | 79 | break; |
80 | default: | ||
81 | return -EINVAL; | ||
80 | } | 82 | } |
81 | 83 | ||
82 | writel(v, MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + | 84 | writel(v, MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + |