Merge branch 'clksrc' into devel

Conflicts:
	arch/arm/mach-vexpress/v2m.c
	arch/arm/plat-omap/counter_32k.c
	arch/arm/plat-versatile/Makefile

1 files changed, 17 insertions, 10 deletions

diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c
index 558cdfaf76b6..07f23bb42bed 100644
--- a/arch/arm/plat-iop/time.c
+++ b/arch/arm/plat-iop/time.c
@@ -17,6 +17,7 @@
 #include <linux/interrupt.h>
 #include <linux/time.h>
 #include <linux/init.h>
+#include <linux/sched.h>
 #include <linux/timex.h>
 #include <linux/sched.h>
 #include <linux/io.h>
@@ -24,6 +25,7 @@
 #include <linux/clockchips.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
+#include <asm/sched_clock.h>
 #include <asm/uaccess.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
@@ -50,15 +52,21 @@ static struct clocksource iop_clocksource = {
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
+static DEFINE_CLOCK_DATA(cd);
+
 /*
  * IOP sched_clock() implementation via its clocksource.
  */
-unsigned long long sched_clock(void)
+unsigned long long notrace sched_clock(void)
 {
-        cycle_t cyc = iop_clocksource_read(NULL);
-        struct clocksource *cs = &iop_clocksource;
+        u32 cyc = 0xffffffffu - read_tcr1();
+        return cyc_to_sched_clock(&cd, cyc, (u32)~0);
+}
 
-        return clocksource_cyc2ns(cyc, cs->mult, cs->shift);
+static void notrace iop_update_sched_clock(void)
+{
+        u32 cyc = 0xffffffffu - read_tcr1();
+        update_sched_clock(&cd, cyc, (u32)~0);
 }
 
 /*
@@ -88,6 +96,7 @@ static void iop_set_mode(enum clock_event_mode mode,
         case CLOCK_EVT_MODE_PERIODIC:
                 write_tmr0(tmr & ~IOP_TMR_EN);
                 write_tcr0(ticks_per_jiffy - 1);
+                write_trr0(ticks_per_jiffy - 1);
                 tmr |= (IOP_TMR_RELOAD | IOP_TMR_EN);
                 break;
         case CLOCK_EVT_MODE_ONESHOT:
@@ -143,6 +152,8 @@ void __init iop_init_time(unsigned long tick_rate)
 {
         u32 timer_ctl;
 
+        init_sched_clock(&cd, iop_update_sched_clock, 32, tick_rate);
+
         ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ);
         iop_tick_rate = tick_rate;
 
@@ -153,6 +164,7 @@ void __init iop_init_time(unsigned long tick_rate)
          * Set up interrupting clockevent timer 0.
          */
         write_tmr0(timer_ctl & ~IOP_TMR_EN);
+        write_tisr(1);
         setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq);
         clockevents_calc_mult_shift(&iop_clockevent,
                                     tick_rate, IOP_MIN_RANGE);
@@ -162,9 +174,6 @@ void __init iop_init_time(unsigned long tick_rate)
                 clockevent_delta2ns(0xf, &iop_clockevent);
         iop_clockevent.cpumask = cpumask_of(0);
         clockevents_register_device(&iop_clockevent);
-        write_trr0(ticks_per_jiffy - 1);
-        write_tcr0(ticks_per_jiffy - 1);
-        write_tmr0(timer_ctl);
 
         /*
          * Set up free-running clocksource timer 1.
@@ -172,7 +181,5 @@ void __init iop_init_time(unsigned long tick_rate)
         write_trr1(0xffffffff);
         write_tcr1(0xffffffff);
         write_tmr1(timer_ctl);
-        clocksource_calc_mult_shift(&iop_clocksource, tick_rate,
-                                    IOP_MIN_RANGE);
-        clocksource_register(&iop_clocksource);
+        clocksource_register_hz(&iop_clocksource, tick_rate);
 }