[ARM] 3825/1: iop3xx: use cp6 enable/disable macros

Add CP6 enable/disable sequences to the timekeeping code and the IRQ
code.  As a result, we can't depend on CP6 access being enabled when
we enter get_irqnr_and_base anymore, so switch the latter over to
using memory-mapped accesses for now.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 4 insertions, 0 deletions

diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c
index 5730a0d7ed67..bed20f3669f4 100644
--- a/arch/arm/plat-iop/time.c
+++ b/arch/arm/plat-iop/time.c
@@ -51,7 +51,9 @@ iop3xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 {
         write_seqlock(&xtime_lock);
 
+        iop3xx_cp6_enable();
         asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (1));
+        iop3xx_cp6_disable();
 
         while ((signed long)(next_jiffy_time - *IOP3XX_TU_TCR1)
                                                         >= ticks_per_jiffy) {
@@ -85,10 +87,12 @@ void __init iop3xx_init_time(unsigned long tick_rate)
          * We use timer 0 for our timer interrupt, and timer 1 as
          * monotonic counter for tracking missed jiffies.
          */
+        iop3xx_cp6_enable();
         asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (ticks_per_jiffy - 1));
         asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (timer_ctl));
         asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (0xffffffff));
         asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (timer_ctl));
+        iop3xx_cp6_disable();
 
         setup_irq(IRQ_IOP3XX_TIMER0, &iop3xx_timer_irq);
 }