[ARM] 5487/1: ARM errata: Stale prediction on replaced interworking branch

This patch adds the workaround for the 430973 Cortex-A8 (r1p0..r1p2)
erratum. The BTAC/BTB is now flushed at every context switch.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 8 insertions, 0 deletions

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index d1ebec42521d..fc81159596fe 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -95,6 +95,9 @@ ENTRY(cpu_v7_switch_mm)
         mov     r2, #0
         ldr     r1, [r1, #MM_CONTEXT_ID]        @ get mm->context.id
         orr     r0, r0, #TTB_FLAGS
+#ifdef CONFIG_ARM_ERRATA_430973
+        mcr     p15, 0, r2, c7, c5, 6           @ flush BTAC/BTB
+#endif
         mcr     p15, 0, r2, c13, c0, 1          @ set reserved context ID
         isb
 1:      mcr     p15, 0, r0, c2, c0, 0           @ set TTB 0
@@ -180,6 +183,11 @@ __v7_setup:
         stmia   r12, {r0-r5, r7, r9, r11, lr}
         bl      v7_flush_dcache_all
         ldmia   r12, {r0-r5, r7, r9, r11, lr}
+#ifdef CONFIG_ARM_ERRATA_430973
+        mrc     p15, 0, r10, c1, c0, 1          @ read aux control register
+        orr     r10, r10, #(1 << 6)             @ set IBE to 1
+        mcr     p15, 0, r10, c1, c0, 1          @ write aux control register
+#endif
         mov     r10, #0
 #ifdef HARVARD_CACHE
         mcr     p15, 0, r10, c7, c5, 0          @ I+BTB cache invalidate