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authorRussell King <rmk+kernel@arm.linux.org.uk>2015-04-03 06:10:46 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2015-04-14 17:26:51 -0400
commit5aca370826a2487aaaae5db31f6bb0b906e9755f (patch)
tree345f23517edaff16eaeb7620bbf9030c83a16f20 /arch/arm/mm
parent89c6bc5884e52ec004f03071f268ba3f27003aba (diff)
ARM: cache-v7: use movw/movt instructions
We always build cache-v7.S for ARMv7, so we can use the ARMv7 16-bit move instructions to load large constants, rather than using constants in a literal pool. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm')
-rw-r--r--arch/arm/mm/cache-v7.S11
1 files changed, 6 insertions, 5 deletions
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index b966656d2c2d..30c81e7d6aaa 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -36,10 +36,10 @@ ENTRY(v7_invalidate_l1)
36 mcr p15, 2, r0, c0, c0, 0 36 mcr p15, 2, r0, c0, c0, 0
37 mrc p15, 1, r0, c0, c0, 0 37 mrc p15, 1, r0, c0, c0, 0
38 38
39 ldr r1, =0x7fff 39 movw r1, #0x7fff
40 and r2, r1, r0, lsr #13 40 and r2, r1, r0, lsr #13
41 41
42 ldr r1, =0x3ff 42 movw r1, #0x3ff
43 43
44 and r3, r1, r0, lsr #3 @ NumWays - 1 44 and r3, r1, r0, lsr #3 @ NumWays - 1
45 add r2, r2, #1 @ NumSets 45 add r2, r2, #1 @ NumSets
@@ -95,7 +95,8 @@ ENTRY(v7_flush_dcache_louis)
95#ifdef CONFIG_ARM_ERRATA_643719 95#ifdef CONFIG_ARM_ERRATA_643719
96 ALT_SMP(mrceq p15, 0, r2, c0, c0, 0) @ read main ID register 96 ALT_SMP(mrceq p15, 0, r2, c0, c0, 0) @ read main ID register
97 ALT_UP(reteq lr) @ LoUU is zero, so nothing to do 97 ALT_UP(reteq lr) @ LoUU is zero, so nothing to do
98 ldreq r1, =0x410fc090 @ ID of ARM Cortex A9 r0p? 98 movweq r1, #:lower16:0x410fc090 @ ID of ARM Cortex A9 r0p?
99 movteq r1, #:upper16:0x410fc090
99 biceq r2, r2, #0x0000000f @ clear minor revision number 100 biceq r2, r2, #0x0000000f @ clear minor revision number
100 teqeq r2, r1 @ test for errata affected core and if so... 101 teqeq r2, r1 @ test for errata affected core and if so...
101 orreqs r3, #(1 << 21) @ fix LoUIS value (and set flags state to 'ne') 102 orreqs r3, #(1 << 21) @ fix LoUIS value (and set flags state to 'ne')
@@ -140,10 +141,10 @@ flush_levels:
140#endif 141#endif
141 and r2, r1, #7 @ extract the length of the cache lines 142 and r2, r1, #7 @ extract the length of the cache lines
142 add r2, r2, #4 @ add 4 (line length offset) 143 add r2, r2, #4 @ add 4 (line length offset)
143 ldr r4, =0x3ff 144 movw r4, #0x3ff
144 ands r4, r4, r1, lsr #3 @ find maximum number on the way size 145 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
145 clz r5, r4 @ find bit position of way size increment 146 clz r5, r4 @ find bit position of way size increment
146 ldr r7, =0x7fff 147 movw r7, #0x7fff
147 ands r7, r7, r1, lsr #13 @ extract max number of the index size 148 ands r7, r7, r1, lsr #13 @ extract max number of the index size
148loop1: 149loop1:
149 mov r9, r7 @ create working copy of max index 150 mov r9, r7 @ create working copy of max index