diff options
author | Marek Szyprowski <m.szyprowski@samsung.com> | 2015-01-08 01:49:41 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2015-01-16 09:35:26 -0500 |
commit | 00218241aa0846e75d31b1dbadb5f8a76be1cc97 (patch) | |
tree | 98c70e0fe37d7f06e8d68ef47893004c271c4938 /arch/arm/mm | |
parent | 944e9df1d4f71f946aa044abc00726346e3c597c (diff) |
ARM: 8258/1: l2c: use l2c_write_sec() for restoring latency and filter regs
All four register for latency and filter settings cannot be written in
non-secure mode and they should go through l2c_write_sec(). More on this
can be found in CoreLink Level 2 Cache Controller L2C-310 Technical
Reference Manual, 3.2. Register summary, table 3.1. This have been checked
the TRM for r3p3, but it should be uniform for all revisions.
Reported-by: Nishanth Menon <nm@ti.com>
Suggested-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Tested-by: Nishanth Menon <nm@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm')
-rw-r--r-- | arch/arm/mm/cache-l2x0.c | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 5e65ca8dea62..b83c401ca50c 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c | |||
@@ -623,14 +623,14 @@ static void l2c310_resume(void) | |||
623 | unsigned revision; | 623 | unsigned revision; |
624 | 624 | ||
625 | /* restore pl310 setup */ | 625 | /* restore pl310 setup */ |
626 | writel_relaxed(l2x0_saved_regs.tag_latency, | 626 | l2c_write_sec(l2x0_saved_regs.tag_latency, base, |
627 | base + L310_TAG_LATENCY_CTRL); | 627 | L310_TAG_LATENCY_CTRL); |
628 | writel_relaxed(l2x0_saved_regs.data_latency, | 628 | l2c_write_sec(l2x0_saved_regs.data_latency, base, |
629 | base + L310_DATA_LATENCY_CTRL); | 629 | L310_DATA_LATENCY_CTRL); |
630 | writel_relaxed(l2x0_saved_regs.filter_end, | 630 | l2c_write_sec(l2x0_saved_regs.filter_end, base, |
631 | base + L310_ADDR_FILTER_END); | 631 | L310_ADDR_FILTER_END); |
632 | writel_relaxed(l2x0_saved_regs.filter_start, | 632 | l2c_write_sec(l2x0_saved_regs.filter_start, base, |
633 | base + L310_ADDR_FILTER_START); | 633 | L310_ADDR_FILTER_START); |
634 | 634 | ||
635 | revision = readl_relaxed(base + L2X0_CACHE_ID) & | 635 | revision = readl_relaxed(base + L2X0_CACHE_ID) & |
636 | L2X0_CACHE_ID_RTL_MASK; | 636 | L2X0_CACHE_ID_RTL_MASK; |
@@ -1135,28 +1135,28 @@ static void __init l2c310_of_parse(const struct device_node *np, | |||
1135 | 1135 | ||
1136 | of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag)); | 1136 | of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag)); |
1137 | if (tag[0] && tag[1] && tag[2]) | 1137 | if (tag[0] && tag[1] && tag[2]) |
1138 | writel_relaxed( | 1138 | l2c_write_sec( |
1139 | L310_LATENCY_CTRL_RD(tag[0] - 1) | | 1139 | L310_LATENCY_CTRL_RD(tag[0] - 1) | |
1140 | L310_LATENCY_CTRL_WR(tag[1] - 1) | | 1140 | L310_LATENCY_CTRL_WR(tag[1] - 1) | |
1141 | L310_LATENCY_CTRL_SETUP(tag[2] - 1), | 1141 | L310_LATENCY_CTRL_SETUP(tag[2] - 1), |
1142 | l2x0_base + L310_TAG_LATENCY_CTRL); | 1142 | l2x0_base, L310_TAG_LATENCY_CTRL); |
1143 | 1143 | ||
1144 | of_property_read_u32_array(np, "arm,data-latency", | 1144 | of_property_read_u32_array(np, "arm,data-latency", |
1145 | data, ARRAY_SIZE(data)); | 1145 | data, ARRAY_SIZE(data)); |
1146 | if (data[0] && data[1] && data[2]) | 1146 | if (data[0] && data[1] && data[2]) |
1147 | writel_relaxed( | 1147 | l2c_write_sec( |
1148 | L310_LATENCY_CTRL_RD(data[0] - 1) | | 1148 | L310_LATENCY_CTRL_RD(data[0] - 1) | |
1149 | L310_LATENCY_CTRL_WR(data[1] - 1) | | 1149 | L310_LATENCY_CTRL_WR(data[1] - 1) | |
1150 | L310_LATENCY_CTRL_SETUP(data[2] - 1), | 1150 | L310_LATENCY_CTRL_SETUP(data[2] - 1), |
1151 | l2x0_base + L310_DATA_LATENCY_CTRL); | 1151 | l2x0_base, L310_DATA_LATENCY_CTRL); |
1152 | 1152 | ||
1153 | of_property_read_u32_array(np, "arm,filter-ranges", | 1153 | of_property_read_u32_array(np, "arm,filter-ranges", |
1154 | filter, ARRAY_SIZE(filter)); | 1154 | filter, ARRAY_SIZE(filter)); |
1155 | if (filter[1]) { | 1155 | if (filter[1]) { |
1156 | writel_relaxed(ALIGN(filter[0] + filter[1], SZ_1M), | 1156 | l2c_write_sec(ALIGN(filter[0] + filter[1], SZ_1M), |
1157 | l2x0_base + L310_ADDR_FILTER_END); | 1157 | l2x0_base, L310_ADDR_FILTER_END); |
1158 | writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L310_ADDR_FILTER_EN, | 1158 | l2c_write_sec((filter[0] & ~(SZ_1M - 1)) | L310_ADDR_FILTER_EN, |
1159 | l2x0_base + L310_ADDR_FILTER_START); | 1159 | l2x0_base, L310_ADDR_FILTER_START); |
1160 | } | 1160 | } |
1161 | 1161 | ||
1162 | ret = l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_512K); | 1162 | ret = l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_512K); |