diff options
author | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-01-08 11:18:37 -0500 |
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committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-01-08 11:18:37 -0500 |
commit | 0de9a00fd6e0a137c63fbbfb6012bf34cc0ab7c4 (patch) | |
tree | bda182d9407e32354620e9188258c86cad2e3813 /arch/arm/mm | |
parent | 22325525d8bb1478daddefec1b762e7882bcd515 (diff) | |
parent | d13fecd0293d55a4bcb8a31078216504192d8ce0 (diff) |
Merge branch 'fix' of git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6
Diffstat (limited to 'arch/arm/mm')
-rw-r--r-- | arch/arm/mm/cache-xsc3l2.c | 11 | ||||
-rw-r--r-- | arch/arm/mm/proc-xsc3.S | 7 |
2 files changed, 12 insertions, 6 deletions
diff --git a/arch/arm/mm/cache-xsc3l2.c b/arch/arm/mm/cache-xsc3l2.c index 5d180cb0bd94..c3154928bccd 100644 --- a/arch/arm/mm/cache-xsc3l2.c +++ b/arch/arm/mm/cache-xsc3l2.c | |||
@@ -221,15 +221,14 @@ static int __init xsc3_l2_init(void) | |||
221 | if (!cpu_is_xsc3() || !xsc3_l2_present()) | 221 | if (!cpu_is_xsc3() || !xsc3_l2_present()) |
222 | return 0; | 222 | return 0; |
223 | 223 | ||
224 | if (!(get_cr() & CR_L2)) { | 224 | if (get_cr() & CR_L2) { |
225 | pr_info("XScale3 L2 cache enabled.\n"); | 225 | pr_info("XScale3 L2 cache enabled.\n"); |
226 | adjust_cr(CR_L2, CR_L2); | ||
227 | xsc3_l2_inv_all(); | 226 | xsc3_l2_inv_all(); |
228 | } | ||
229 | 227 | ||
230 | outer_cache.inv_range = xsc3_l2_inv_range; | 228 | outer_cache.inv_range = xsc3_l2_inv_range; |
231 | outer_cache.clean_range = xsc3_l2_clean_range; | 229 | outer_cache.clean_range = xsc3_l2_clean_range; |
232 | outer_cache.flush_range = xsc3_l2_flush_range; | 230 | outer_cache.flush_range = xsc3_l2_flush_range; |
231 | } | ||
233 | 232 | ||
234 | return 0; | 233 | return 0; |
235 | } | 234 | } |
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index 96456f548798..8e4f6dca8997 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S | |||
@@ -407,6 +407,13 @@ __xsc3_setup: | |||
407 | 407 | ||
408 | adr r5, xsc3_crval | 408 | adr r5, xsc3_crval |
409 | ldmia r5, {r5, r6} | 409 | ldmia r5, {r5, r6} |
410 | |||
411 | #ifdef CONFIG_CACHE_XSC3L2 | ||
412 | mrc p15, 1, r0, c0, c0, 1 @ get L2 present information | ||
413 | ands r0, r0, #0xf8 | ||
414 | orrne r6, r6, #(1 << 26) @ enable L2 if present | ||
415 | #endif | ||
416 | |||
410 | mrc p15, 0, r0, c1, c0, 0 @ get control register | 417 | mrc p15, 0, r0, c1, c0, 0 @ get control register |
411 | bic r0, r0, r5 @ ..V. ..R. .... ..A. | 418 | bic r0, r0, r5 @ ..V. ..R. .... ..A. |
412 | orr r0, r0, r6 @ ..VI Z..S .... .C.M (mmu) | 419 | orr r0, r0, r6 @ ..VI Z..S .... .C.M (mmu) |