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authorNicolas Pitre <nico@cam.org>2006-02-01 14:26:01 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-02-01 14:26:01 -0500
commit8a052e0bc25ff52f17b3dff150846ca9eb969162 (patch)
tree607355bc9ce1ac2d6f5611287cf89fa473d48d02 /arch/arm/mm
parent62500d1f8eadff078cca462dc4df035a29180383 (diff)
[ARM] 3293/1: don't invalidate the whole I-cache with xscale_coherent_user_range
Patch from Nicolas Pitre The mini I-cache issue is valid only for kernel space since debuggers would not fly if they used user space addresses for their stubs. Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm')
-rw-r--r--arch/arm/mm/proc-xscale.S16
1 files changed, 11 insertions, 5 deletions
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 861b35947280..2d3823ec3153 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -241,7 +241,15 @@ ENTRY(xscale_flush_user_cache_range)
241 * it also trashes the mini I-cache used by JTAG debuggers. 241 * it also trashes the mini I-cache used by JTAG debuggers.
242 */ 242 */
243ENTRY(xscale_coherent_kern_range) 243ENTRY(xscale_coherent_kern_range)
244 /* FALLTHROUGH */ 244 bic r0, r0, #CACHELINESIZE - 1
2451: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
246 add r0, r0, #CACHELINESIZE
247 cmp r0, r1
248 blo 1b
249 mov r0, #0
250 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
251 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
252 mov pc, lr
245 253
246/* 254/*
247 * coherent_user_range(start, end) 255 * coherent_user_range(start, end)
@@ -252,18 +260,16 @@ ENTRY(xscale_coherent_kern_range)
252 * 260 *
253 * - start - virtual start address 261 * - start - virtual start address
254 * - end - virtual end address 262 * - end - virtual end address
255 *
256 * Note: single I-cache line invalidation isn't used here since
257 * it also trashes the mini I-cache used by JTAG debuggers.
258 */ 263 */
259ENTRY(xscale_coherent_user_range) 264ENTRY(xscale_coherent_user_range)
260 bic r0, r0, #CACHELINESIZE - 1 265 bic r0, r0, #CACHELINESIZE - 1
2611: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 2661: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
267 mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache entry
262 add r0, r0, #CACHELINESIZE 268 add r0, r0, #CACHELINESIZE
263 cmp r0, r1 269 cmp r0, r1
264 blo 1b 270 blo 1b
265 mov r0, #0 271 mov r0, #0
266 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB 272 mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB
267 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 273 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
268 mov pc, lr 274 mov pc, lr
269 275