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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2008-10-09 16:31:56 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-10-09 16:31:56 -0400
commit6a4690c22f5da1eb1c898b61b6a80da52fbd976f (patch)
treea03891a32abe0da191fb765fe669a597e07423c6 /arch/arm/mm
parent90bb28b0644f7324f8bd1feb27b35146e6785ba2 (diff)
parent8ec53663d2698076468b3e1edc4e1b418bd54de3 (diff)
Merge branch 'ptebits' into devel
Conflicts: arch/arm/Kconfig
Diffstat (limited to 'arch/arm/mm')
-rw-r--r--arch/arm/mm/copypage-v4mc.c2
-rw-r--r--arch/arm/mm/copypage-xscale.c2
-rw-r--r--arch/arm/mm/fault-armv.c11
-rw-r--r--arch/arm/mm/ioremap.c3
-rw-r--r--arch/arm/mm/mm.h1
-rw-r--r--arch/arm/mm/mmu.c74
-rw-r--r--arch/arm/mm/proc-arm1020.S26
-rw-r--r--arch/arm/mm/proc-arm1020e.S26
-rw-r--r--arch/arm/mm/proc-arm1022.S26
-rw-r--r--arch/arm/mm/proc-arm1026.S26
-rw-r--r--arch/arm/mm/proc-arm6_7.S27
-rw-r--r--arch/arm/mm/proc-arm720.S25
-rw-r--r--arch/arm/mm/proc-arm740.S2
-rw-r--r--arch/arm/mm/proc-arm7tdmi.S2
-rw-r--r--arch/arm/mm/proc-arm920.S28
-rw-r--r--arch/arm/mm/proc-arm922.S26
-rw-r--r--arch/arm/mm/proc-arm925.S26
-rw-r--r--arch/arm/mm/proc-arm926.S26
-rw-r--r--arch/arm/mm/proc-arm940.S2
-rw-r--r--arch/arm/mm/proc-arm946.S2
-rw-r--r--arch/arm/mm/proc-arm9tdmi.S2
-rw-r--r--arch/arm/mm/proc-feroceon.S21
-rw-r--r--arch/arm/mm/proc-macros.S170
-rw-r--r--arch/arm/mm/proc-sa110.S21
-rw-r--r--arch/arm/mm/proc-sa1100.S21
-rw-r--r--arch/arm/mm/proc-v6.S42
-rw-r--r--arch/arm/mm/proc-v7.S29
-rw-r--r--arch/arm/mm/proc-xsc3.S56
-rw-r--r--arch/arm/mm/proc-xscale.S76
29 files changed, 333 insertions, 468 deletions
diff --git a/arch/arm/mm/copypage-v4mc.c b/arch/arm/mm/copypage-v4mc.c
index ded0e96d069d..8d33e2549344 100644
--- a/arch/arm/mm/copypage-v4mc.c
+++ b/arch/arm/mm/copypage-v4mc.c
@@ -28,7 +28,7 @@
28 * specific hacks for copying pages efficiently. 28 * specific hacks for copying pages efficiently.
29 */ 29 */
30#define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \ 30#define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \
31 L_PTE_CACHEABLE) 31 L_PTE_MT_MINICACHE)
32 32
33static DEFINE_SPINLOCK(minicache_lock); 33static DEFINE_SPINLOCK(minicache_lock);
34 34
diff --git a/arch/arm/mm/copypage-xscale.c b/arch/arm/mm/copypage-xscale.c
index 2e455f82a4d5..bad49331bbf9 100644
--- a/arch/arm/mm/copypage-xscale.c
+++ b/arch/arm/mm/copypage-xscale.c
@@ -30,7 +30,7 @@
30#define COPYPAGE_MINICACHE 0xffff8000 30#define COPYPAGE_MINICACHE 0xffff8000
31 31
32#define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \ 32#define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \
33 L_PTE_CACHEABLE) 33 L_PTE_MT_MINICACHE)
34 34
35static DEFINE_SPINLOCK(minicache_lock); 35static DEFINE_SPINLOCK(minicache_lock);
36 36
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index af6ed6ef9a81..81d0b8772de3 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -23,7 +23,7 @@
23#include <asm/pgtable.h> 23#include <asm/pgtable.h>
24#include <asm/tlbflush.h> 24#include <asm/tlbflush.h>
25 25
26static unsigned long shared_pte_mask = L_PTE_CACHEABLE; 26static unsigned long shared_pte_mask = L_PTE_MT_BUFFERABLE;
27 27
28/* 28/*
29 * We take the easy way out of this problem - we make the 29 * We take the easy way out of this problem - we make the
@@ -65,9 +65,10 @@ static int adjust_pte(struct vm_area_struct *vma, unsigned long address)
65 * If this page isn't present, or is already setup to 65 * If this page isn't present, or is already setup to
66 * fault (ie, is old), we can safely ignore any issues. 66 * fault (ie, is old), we can safely ignore any issues.
67 */ 67 */
68 if (ret && pte_val(entry) & shared_pte_mask) { 68 if (ret && (pte_val(entry) & L_PTE_MT_MASK) != shared_pte_mask) {
69 flush_cache_page(vma, address, pte_pfn(entry)); 69 flush_cache_page(vma, address, pte_pfn(entry));
70 pte_val(entry) &= ~shared_pte_mask; 70 pte_val(entry) &= ~L_PTE_MT_MASK;
71 pte_val(entry) |= shared_pte_mask;
71 set_pte_at(vma->vm_mm, address, pte, entry); 72 set_pte_at(vma->vm_mm, address, pte, entry);
72 flush_tlb_page(vma, address); 73 flush_tlb_page(vma, address);
73 } 74 }
@@ -199,7 +200,7 @@ void __init check_writebuffer_bugs(void)
199 unsigned long *p1, *p2; 200 unsigned long *p1, *p2;
200 pgprot_t prot = __pgprot(L_PTE_PRESENT|L_PTE_YOUNG| 201 pgprot_t prot = __pgprot(L_PTE_PRESENT|L_PTE_YOUNG|
201 L_PTE_DIRTY|L_PTE_WRITE| 202 L_PTE_DIRTY|L_PTE_WRITE|
202 L_PTE_BUFFERABLE); 203 L_PTE_MT_BUFFERABLE);
203 204
204 p1 = vmap(&page, 1, VM_IOREMAP, prot); 205 p1 = vmap(&page, 1, VM_IOREMAP, prot);
205 p2 = vmap(&page, 1, VM_IOREMAP, prot); 206 p2 = vmap(&page, 1, VM_IOREMAP, prot);
@@ -220,7 +221,7 @@ void __init check_writebuffer_bugs(void)
220 221
221 if (v) { 222 if (v) {
222 printk("failed, %s\n", reason); 223 printk("failed, %s\n", reason);
223 shared_pte_mask |= L_PTE_BUFFERABLE; 224 shared_pte_mask = L_PTE_MT_UNCACHED;
224 } else { 225 } else {
225 printk("ok\n"); 226 printk("ok\n");
226 } 227 }
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 8a41912ec7c5..18373f73f2fc 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -56,8 +56,7 @@ static int remap_area_pte(pmd_t *pmd, unsigned long addr, unsigned long end,
56 if (!pte_none(*pte)) 56 if (!pte_none(*pte))
57 goto bad; 57 goto bad;
58 58
59 set_pte_ext(pte, pfn_pte(phys_addr >> PAGE_SHIFT, prot), 59 set_pte_ext(pte, pfn_pte(phys_addr >> PAGE_SHIFT, prot), 0);
60 type->prot_pte_ext);
61 phys_addr += PAGE_SIZE; 60 phys_addr += PAGE_SIZE;
62 } while (pte++, addr += PAGE_SIZE, addr != end); 61 } while (pte++, addr += PAGE_SIZE, addr != end);
63 return 0; 62 return 0;
diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
index 96590104ba0f..5d9f53907b4e 100644
--- a/arch/arm/mm/mm.h
+++ b/arch/arm/mm/mm.h
@@ -18,7 +18,6 @@ static inline pmd_t *pmd_off_k(unsigned long virt)
18 18
19struct mem_type { 19struct mem_type {
20 unsigned int prot_pte; 20 unsigned int prot_pte;
21 unsigned int prot_pte_ext;
22 unsigned int prot_l1; 21 unsigned int prot_l1;
23 unsigned int prot_sect; 22 unsigned int prot_sect;
24 unsigned int domain; 23 unsigned int domain;
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index e7af83e569d7..8ba754064559 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -66,27 +66,27 @@ static struct cachepolicy cache_policies[] __initdata = {
66 .policy = "uncached", 66 .policy = "uncached",
67 .cr_mask = CR_W|CR_C, 67 .cr_mask = CR_W|CR_C,
68 .pmd = PMD_SECT_UNCACHED, 68 .pmd = PMD_SECT_UNCACHED,
69 .pte = 0, 69 .pte = L_PTE_MT_UNCACHED,
70 }, { 70 }, {
71 .policy = "buffered", 71 .policy = "buffered",
72 .cr_mask = CR_C, 72 .cr_mask = CR_C,
73 .pmd = PMD_SECT_BUFFERED, 73 .pmd = PMD_SECT_BUFFERED,
74 .pte = PTE_BUFFERABLE, 74 .pte = L_PTE_MT_BUFFERABLE,
75 }, { 75 }, {
76 .policy = "writethrough", 76 .policy = "writethrough",
77 .cr_mask = 0, 77 .cr_mask = 0,
78 .pmd = PMD_SECT_WT, 78 .pmd = PMD_SECT_WT,
79 .pte = PTE_CACHEABLE, 79 .pte = L_PTE_MT_WRITETHROUGH,
80 }, { 80 }, {
81 .policy = "writeback", 81 .policy = "writeback",
82 .cr_mask = 0, 82 .cr_mask = 0,
83 .pmd = PMD_SECT_WB, 83 .pmd = PMD_SECT_WB,
84 .pte = PTE_BUFFERABLE|PTE_CACHEABLE, 84 .pte = L_PTE_MT_WRITEBACK,
85 }, { 85 }, {
86 .policy = "writealloc", 86 .policy = "writealloc",
87 .cr_mask = 0, 87 .cr_mask = 0,
88 .pmd = PMD_SECT_WBWA, 88 .pmd = PMD_SECT_WBWA,
89 .pte = PTE_BUFFERABLE|PTE_CACHEABLE, 89 .pte = L_PTE_MT_WRITEALLOC,
90 } 90 }
91}; 91};
92 92
@@ -184,29 +184,28 @@ void adjust_cr(unsigned long mask, unsigned long set)
184 184
185static struct mem_type mem_types[] = { 185static struct mem_type mem_types[] = {
186 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */ 186 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
187 .prot_pte = PROT_PTE_DEVICE, 187 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
188 L_PTE_SHARED,
188 .prot_l1 = PMD_TYPE_TABLE, 189 .prot_l1 = PMD_TYPE_TABLE,
189 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_UNCACHED, 190 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_UNCACHED,
190 .domain = DOMAIN_IO, 191 .domain = DOMAIN_IO,
191 }, 192 },
192 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */ 193 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
193 .prot_pte = PROT_PTE_DEVICE, 194 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
194 .prot_pte_ext = PTE_EXT_TEX(2),
195 .prot_l1 = PMD_TYPE_TABLE, 195 .prot_l1 = PMD_TYPE_TABLE,
196 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_TEX(2), 196 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_TEX(2),
197 .domain = DOMAIN_IO, 197 .domain = DOMAIN_IO,
198 }, 198 },
199 [MT_DEVICE_CACHED] = { /* ioremap_cached */ 199 [MT_DEVICE_CACHED] = { /* ioremap_cached */
200 .prot_pte = PROT_PTE_DEVICE | L_PTE_CACHEABLE | L_PTE_BUFFERABLE, 200 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
201 .prot_l1 = PMD_TYPE_TABLE, 201 .prot_l1 = PMD_TYPE_TABLE,
202 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB, 202 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
203 .domain = DOMAIN_IO, 203 .domain = DOMAIN_IO,
204 }, 204 },
205 [MT_DEVICE_IXP2000] = { /* IXP2400 requires XCB=101 for on-chip I/O */ 205 [MT_DEVICE_WC] = { /* ioremap_wc */
206 .prot_pte = PROT_PTE_DEVICE, 206 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
207 .prot_l1 = PMD_TYPE_TABLE, 207 .prot_l1 = PMD_TYPE_TABLE,
208 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_BUFFERABLE | 208 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_BUFFERABLE,
209 PMD_SECT_TEX(1),
210 .domain = DOMAIN_IO, 209 .domain = DOMAIN_IO,
211 }, 210 },
212 [MT_CACHECLEAN] = { 211 [MT_CACHECLEAN] = {
@@ -251,7 +250,7 @@ static void __init build_mem_type_table(void)
251{ 250{
252 struct cachepolicy *cp; 251 struct cachepolicy *cp;
253 unsigned int cr = get_cr(); 252 unsigned int cr = get_cr();
254 unsigned int user_pgprot, kern_pgprot; 253 unsigned int user_pgprot, kern_pgprot, vecs_pgprot;
255 int cpu_arch = cpu_architecture(); 254 int cpu_arch = cpu_architecture();
256 int i; 255 int i;
257 256
@@ -269,6 +268,20 @@ static void __init build_mem_type_table(void)
269 cachepolicy = CPOLICY_WRITEBACK; 268 cachepolicy = CPOLICY_WRITEBACK;
270 ecc_mask = 0; 269 ecc_mask = 0;
271 } 270 }
271#ifdef CONFIG_SMP
272 cachepolicy = CPOLICY_WRITEALLOC;
273#endif
274
275 /*
276 * On non-Xscale3 ARMv5-and-older systems, use CB=01
277 * (Uncached/Buffered) for ioremap_wc() mappings. On XScale3
278 * and ARMv6+, use TEXCB=00100 mappings (Inner/Outer Uncacheable
279 * in xsc3 parlance, Uncached Normal in ARMv6 parlance).
280 */
281 if (cpu_is_xsc3() || cpu_arch >= CPU_ARCH_ARMv6) {
282 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
283 mem_types[MT_DEVICE_WC].prot_sect &= ~PMD_SECT_BUFFERABLE;
284 }
272 285
273 /* 286 /*
274 * ARMv5 and lower, bit 4 must be set for page tables. 287 * ARMv5 and lower, bit 4 must be set for page tables.
@@ -290,7 +303,15 @@ static void __init build_mem_type_table(void)
290 } 303 }
291 304
292 cp = &cache_policies[cachepolicy]; 305 cp = &cache_policies[cachepolicy];
293 kern_pgprot = user_pgprot = cp->pte; 306 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
307
308#ifndef CONFIG_SMP
309 /*
310 * Only use write-through for non-SMP systems
311 */
312 if (cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
313 vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
314#endif
294 315
295 /* 316 /*
296 * Enable CPU-specific coherency if supported. 317 * Enable CPU-specific coherency if supported.
@@ -318,7 +339,6 @@ static void __init build_mem_type_table(void)
318 /* 339 /*
319 * Mark the device area as "shared device" 340 * Mark the device area as "shared device"
320 */ 341 */
321 mem_types[MT_DEVICE].prot_pte |= L_PTE_BUFFERABLE;
322 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED; 342 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
323 343
324#ifdef CONFIG_SMP 344#ifdef CONFIG_SMP
@@ -327,30 +347,21 @@ static void __init build_mem_type_table(void)
327 */ 347 */
328 user_pgprot |= L_PTE_SHARED; 348 user_pgprot |= L_PTE_SHARED;
329 kern_pgprot |= L_PTE_SHARED; 349 kern_pgprot |= L_PTE_SHARED;
350 vecs_pgprot |= L_PTE_SHARED;
330 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; 351 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
331#endif 352#endif
332 } 353 }
333 354
334 for (i = 0; i < 16; i++) { 355 for (i = 0; i < 16; i++) {
335 unsigned long v = pgprot_val(protection_map[i]); 356 unsigned long v = pgprot_val(protection_map[i]);
336 v = (v & ~(L_PTE_BUFFERABLE|L_PTE_CACHEABLE)) | user_pgprot; 357 protection_map[i] = __pgprot(v | user_pgprot);
337 protection_map[i] = __pgprot(v);
338 } 358 }
339 359
340 mem_types[MT_LOW_VECTORS].prot_pte |= kern_pgprot; 360 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
341 mem_types[MT_HIGH_VECTORS].prot_pte |= kern_pgprot; 361 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
342 362
343 if (cpu_arch >= CPU_ARCH_ARMv5) { 363 if (cpu_arch < CPU_ARCH_ARMv5)
344#ifndef CONFIG_SMP
345 /*
346 * Only use write-through for non-SMP systems
347 */
348 mem_types[MT_LOW_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE;
349 mem_types[MT_HIGH_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE;
350#endif
351 } else {
352 mem_types[MT_MINICLEAN].prot_sect &= ~PMD_SECT_TEX(1); 364 mem_types[MT_MINICLEAN].prot_sect &= ~PMD_SECT_TEX(1);
353 }
354 365
355 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot); 366 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
356 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | 367 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
@@ -398,8 +409,7 @@ static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
398 409
399 pte = pte_offset_kernel(pmd, addr); 410 pte = pte_offset_kernel(pmd, addr);
400 do { 411 do {
401 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 412 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
402 type->prot_pte_ext);
403 pfn++; 413 pfn++;
404 } while (pte++, addr += PAGE_SIZE, addr != end); 414 } while (pte++, addr += PAGE_SIZE, addr != end);
405} 415}
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 5673f4d6113b..b5551bf010aa 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -29,7 +29,7 @@
29#include <linux/init.h> 29#include <linux/init.h>
30#include <asm/assembler.h> 30#include <asm/assembler.h>
31#include <asm/asm-offsets.h> 31#include <asm/asm-offsets.h>
32#include <asm/elf.h> 32#include <asm/hwcap.h>
33#include <asm/pgtable-hwdef.h> 33#include <asm/pgtable-hwdef.h>
34#include <asm/pgtable.h> 34#include <asm/pgtable.h>
35#include <asm/ptrace.h> 35#include <asm/ptrace.h>
@@ -399,29 +399,7 @@ ENTRY(cpu_arm1020_switch_mm)
399 .align 5 399 .align 5
400ENTRY(cpu_arm1020_set_pte_ext) 400ENTRY(cpu_arm1020_set_pte_ext)
401#ifdef CONFIG_MMU 401#ifdef CONFIG_MMU
402 str r1, [r0], #-2048 @ linux version 402 armv3_set_pte_ext
403
404 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
405
406 bic r2, r1, #PTE_SMALL_AP_MASK
407 bic r2, r2, #PTE_TYPE_MASK
408 orr r2, r2, #PTE_TYPE_SMALL
409
410 tst r1, #L_PTE_USER @ User?
411 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
412
413 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
414 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
415
416 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
417 movne r2, #0
418
419#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
420 eor r3, r1, #0x0a @ C & small page?
421 tst r3, #0x0b
422 biceq r2, r2, #4
423#endif
424 str r2, [r0] @ hardware version
425 mov r0, r0 403 mov r0, r0
426#ifndef CONFIG_CPU_DCACHE_DISABLE 404#ifndef CONFIG_CPU_DCACHE_DISABLE
427 mcr p15, 0, r0, c7, c10, 4 405 mcr p15, 0, r0, c7, c10, 4
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 4343fdb0e9e5..8bc6740c29eb 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -29,7 +29,7 @@
29#include <linux/init.h> 29#include <linux/init.h>
30#include <asm/assembler.h> 30#include <asm/assembler.h>
31#include <asm/asm-offsets.h> 31#include <asm/asm-offsets.h>
32#include <asm/elf.h> 32#include <asm/hwcap.h>
33#include <asm/pgtable-hwdef.h> 33#include <asm/pgtable-hwdef.h>
34#include <asm/pgtable.h> 34#include <asm/pgtable.h>
35#include <asm/ptrace.h> 35#include <asm/ptrace.h>
@@ -383,29 +383,7 @@ ENTRY(cpu_arm1020e_switch_mm)
383 .align 5 383 .align 5
384ENTRY(cpu_arm1020e_set_pte_ext) 384ENTRY(cpu_arm1020e_set_pte_ext)
385#ifdef CONFIG_MMU 385#ifdef CONFIG_MMU
386 str r1, [r0], #-2048 @ linux version 386 armv3_set_pte_ext
387
388 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
389
390 bic r2, r1, #PTE_SMALL_AP_MASK
391 bic r2, r2, #PTE_TYPE_MASK
392 orr r2, r2, #PTE_TYPE_SMALL
393
394 tst r1, #L_PTE_USER @ User?
395 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
396
397 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
398 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
399
400 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
401 movne r2, #0
402
403#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
404 eor r3, r1, #0x0a @ C & small page?
405 tst r3, #0x0b
406 biceq r2, r2, #4
407#endif
408 str r2, [r0] @ hardware version
409 mov r0, r0 387 mov r0, r0
410#ifndef CONFIG_CPU_DCACHE_DISABLE 388#ifndef CONFIG_CPU_DCACHE_DISABLE
411 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 389 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index 2a4ea1659e96..2cd03e66c0a3 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -18,7 +18,7 @@
18#include <linux/init.h> 18#include <linux/init.h>
19#include <asm/assembler.h> 19#include <asm/assembler.h>
20#include <asm/asm-offsets.h> 20#include <asm/asm-offsets.h>
21#include <asm/elf.h> 21#include <asm/hwcap.h>
22#include <asm/pgtable-hwdef.h> 22#include <asm/pgtable-hwdef.h>
23#include <asm/pgtable.h> 23#include <asm/pgtable.h>
24#include <asm/ptrace.h> 24#include <asm/ptrace.h>
@@ -365,29 +365,7 @@ ENTRY(cpu_arm1022_switch_mm)
365 .align 5 365 .align 5
366ENTRY(cpu_arm1022_set_pte_ext) 366ENTRY(cpu_arm1022_set_pte_ext)
367#ifdef CONFIG_MMU 367#ifdef CONFIG_MMU
368 str r1, [r0], #-2048 @ linux version 368 armv3_set_pte_ext
369
370 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
371
372 bic r2, r1, #PTE_SMALL_AP_MASK
373 bic r2, r2, #PTE_TYPE_MASK
374 orr r2, r2, #PTE_TYPE_SMALL
375
376 tst r1, #L_PTE_USER @ User?
377 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
378
379 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
380 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
381
382 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
383 movne r2, #0
384
385#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
386 eor r3, r1, #0x0a @ C & small page?
387 tst r3, #0x0b
388 biceq r2, r2, #4
389#endif
390 str r2, [r0] @ hardware version
391 mov r0, r0 369 mov r0, r0
392#ifndef CONFIG_CPU_DCACHE_DISABLE 370#ifndef CONFIG_CPU_DCACHE_DISABLE
393 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 371 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 77a1babd421c..ad961a897f6e 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -18,7 +18,7 @@
18#include <linux/init.h> 18#include <linux/init.h>
19#include <asm/assembler.h> 19#include <asm/assembler.h>
20#include <asm/asm-offsets.h> 20#include <asm/asm-offsets.h>
21#include <asm/elf.h> 21#include <asm/hwcap.h>
22#include <asm/pgtable-hwdef.h> 22#include <asm/pgtable-hwdef.h>
23#include <asm/pgtable.h> 23#include <asm/pgtable.h>
24#include <asm/ptrace.h> 24#include <asm/ptrace.h>
@@ -354,29 +354,7 @@ ENTRY(cpu_arm1026_switch_mm)
354 .align 5 354 .align 5
355ENTRY(cpu_arm1026_set_pte_ext) 355ENTRY(cpu_arm1026_set_pte_ext)
356#ifdef CONFIG_MMU 356#ifdef CONFIG_MMU
357 str r1, [r0], #-2048 @ linux version 357 armv3_set_pte_ext
358
359 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
360
361 bic r2, r1, #PTE_SMALL_AP_MASK
362 bic r2, r2, #PTE_TYPE_MASK
363 orr r2, r2, #PTE_TYPE_SMALL
364
365 tst r1, #L_PTE_USER @ User?
366 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
367
368 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
369 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
370
371 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
372 movne r2, #0
373
374#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
375 eor r3, r1, #0x0a @ C & small page?
376 tst r3, #0x0b
377 biceq r2, r2, #4
378#endif
379 str r2, [r0] @ hardware version
380 mov r0, r0 358 mov r0, r0
381#ifndef CONFIG_CPU_DCACHE_DISABLE 359#ifndef CONFIG_CPU_DCACHE_DISABLE
382 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 360 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index c371fc87776e..80d6e1de069a 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -15,11 +15,13 @@
15#include <linux/init.h> 15#include <linux/init.h>
16#include <asm/assembler.h> 16#include <asm/assembler.h>
17#include <asm/asm-offsets.h> 17#include <asm/asm-offsets.h>
18#include <asm/elf.h> 18#include <asm/hwcap.h>
19#include <asm/pgtable-hwdef.h> 19#include <asm/pgtable-hwdef.h>
20#include <asm/pgtable.h> 20#include <asm/pgtable.h>
21#include <asm/ptrace.h> 21#include <asm/ptrace.h>
22 22
23#include "proc-macros.S"
24
23ENTRY(cpu_arm6_dcache_clean_area) 25ENTRY(cpu_arm6_dcache_clean_area)
24ENTRY(cpu_arm7_dcache_clean_area) 26ENTRY(cpu_arm7_dcache_clean_area)
25 mov pc, lr 27 mov pc, lr
@@ -214,30 +216,13 @@ ENTRY(cpu_arm7_switch_mm)
214 * : r1 = value to set 216 * : r1 = value to set
215 * Purpose : Set a PTE and flush it out of any WB cache 217 * Purpose : Set a PTE and flush it out of any WB cache
216 */ 218 */
217 .align 5 219 .align 5
218ENTRY(cpu_arm6_set_pte_ext) 220ENTRY(cpu_arm6_set_pte_ext)
219ENTRY(cpu_arm7_set_pte_ext) 221ENTRY(cpu_arm7_set_pte_ext)
220#ifdef CONFIG_MMU 222#ifdef CONFIG_MMU
221 str r1, [r0], #-2048 @ linux version 223 armv3_set_pte_ext wc_disable=0
222
223 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
224
225 bic r2, r1, #PTE_SMALL_AP_MASK
226 bic r2, r2, #PTE_TYPE_MASK
227 orr r2, r2, #PTE_TYPE_SMALL
228
229 tst r1, #L_PTE_USER @ User?
230 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
231
232 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
233 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
234
235 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young
236 movne r2, #0
237
238 str r2, [r0] @ hardware version
239#endif /* CONFIG_MMU */ 224#endif /* CONFIG_MMU */
240 mov pc, lr 225 mov pc, lr
241 226
242/* 227/*
243 * Function: _arm6_7_reset 228 * Function: _arm6_7_reset
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index eda733d30455..85ae18695f10 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -36,7 +36,7 @@
36#include <linux/init.h> 36#include <linux/init.h>
37#include <asm/assembler.h> 37#include <asm/assembler.h>
38#include <asm/asm-offsets.h> 38#include <asm/asm-offsets.h>
39#include <asm/elf.h> 39#include <asm/hwcap.h>
40#include <asm/pgtable-hwdef.h> 40#include <asm/pgtable-hwdef.h>
41#include <asm/pgtable.h> 41#include <asm/pgtable.h>
42#include <asm/ptrace.h> 42#include <asm/ptrace.h>
@@ -93,29 +93,12 @@ ENTRY(cpu_arm720_switch_mm)
93 * : r1 = value to set 93 * : r1 = value to set
94 * Purpose : Set a PTE and flush it out of any WB cache 94 * Purpose : Set a PTE and flush it out of any WB cache
95 */ 95 */
96 .align 5 96 .align 5
97ENTRY(cpu_arm720_set_pte_ext) 97ENTRY(cpu_arm720_set_pte_ext)
98#ifdef CONFIG_MMU 98#ifdef CONFIG_MMU
99 str r1, [r0], #-2048 @ linux version 99 armv3_set_pte_ext wc_disable=0
100
101 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
102
103 bic r2, r1, #PTE_SMALL_AP_MASK
104 bic r2, r2, #PTE_TYPE_MASK
105 orr r2, r2, #PTE_TYPE_SMALL
106
107 tst r1, #L_PTE_USER @ User?
108 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
109
110 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
111 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
112
113 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young
114 movne r2, #0
115
116 str r2, [r0] @ hardware version
117#endif 100#endif
118 mov pc, lr 101 mov pc, lr
119 102
120/* 103/*
121 * Function: arm720_reset 104 * Function: arm720_reset
diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S
index 3a57376c8bc9..4f95bee63e95 100644
--- a/arch/arm/mm/proc-arm740.S
+++ b/arch/arm/mm/proc-arm740.S
@@ -12,7 +12,7 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <asm/assembler.h> 13#include <asm/assembler.h>
14#include <asm/asm-offsets.h> 14#include <asm/asm-offsets.h>
15#include <asm/elf.h> 15#include <asm/hwcap.h>
16#include <asm/pgtable-hwdef.h> 16#include <asm/pgtable-hwdef.h>
17#include <asm/pgtable.h> 17#include <asm/pgtable.h>
18#include <asm/ptrace.h> 18#include <asm/ptrace.h>
diff --git a/arch/arm/mm/proc-arm7tdmi.S b/arch/arm/mm/proc-arm7tdmi.S
index 7b3ecdeb5370..93e05fa7bed4 100644
--- a/arch/arm/mm/proc-arm7tdmi.S
+++ b/arch/arm/mm/proc-arm7tdmi.S
@@ -12,7 +12,7 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <asm/assembler.h> 13#include <asm/assembler.h>
14#include <asm/asm-offsets.h> 14#include <asm/asm-offsets.h>
15#include <asm/elf.h> 15#include <asm/hwcap.h>
16#include <asm/pgtable-hwdef.h> 16#include <asm/pgtable-hwdef.h>
17#include <asm/pgtable.h> 17#include <asm/pgtable.h>
18#include <asm/ptrace.h> 18#include <asm/ptrace.h>
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 28cdb060df45..914d688394fc 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -28,7 +28,7 @@
28#include <linux/linkage.h> 28#include <linux/linkage.h>
29#include <linux/init.h> 29#include <linux/init.h>
30#include <asm/assembler.h> 30#include <asm/assembler.h>
31#include <asm/elf.h> 31#include <asm/hwcap.h>
32#include <asm/pgtable-hwdef.h> 32#include <asm/pgtable-hwdef.h>
33#include <asm/pgtable.h> 33#include <asm/pgtable.h>
34#include <asm/page.h> 34#include <asm/page.h>
@@ -351,33 +351,11 @@ ENTRY(cpu_arm920_switch_mm)
351 .align 5 351 .align 5
352ENTRY(cpu_arm920_set_pte_ext) 352ENTRY(cpu_arm920_set_pte_ext)
353#ifdef CONFIG_MMU 353#ifdef CONFIG_MMU
354 str r1, [r0], #-2048 @ linux version 354 armv3_set_pte_ext
355
356 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
357
358 bic r2, r1, #PTE_SMALL_AP_MASK
359 bic r2, r2, #PTE_TYPE_MASK
360 orr r2, r2, #PTE_TYPE_SMALL
361
362 tst r1, #L_PTE_USER @ User?
363 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
364
365 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
366 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
367
368 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
369 movne r2, #0
370
371#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
372 eor r3, r2, #0x0a @ C & small page?
373 tst r3, #0x0b
374 biceq r2, r2, #4
375#endif
376 str r2, [r0] @ hardware version
377 mov r0, r0 355 mov r0, r0
378 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 356 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
379 mcr p15, 0, r0, c7, c10, 4 @ drain WB 357 mcr p15, 0, r0, c7, c10, 4 @ drain WB
380#endif /* CONFIG_MMU */ 358#endif
381 mov pc, lr 359 mov pc, lr
382 360
383 __INIT 361 __INIT
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index 94ddcb4a4b76..51c9c9859e58 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -29,7 +29,7 @@
29#include <linux/linkage.h> 29#include <linux/linkage.h>
30#include <linux/init.h> 30#include <linux/init.h>
31#include <asm/assembler.h> 31#include <asm/assembler.h>
32#include <asm/elf.h> 32#include <asm/hwcap.h>
33#include <asm/pgtable-hwdef.h> 33#include <asm/pgtable-hwdef.h>
34#include <asm/pgtable.h> 34#include <asm/pgtable.h>
35#include <asm/page.h> 35#include <asm/page.h>
@@ -355,29 +355,7 @@ ENTRY(cpu_arm922_switch_mm)
355 .align 5 355 .align 5
356ENTRY(cpu_arm922_set_pte_ext) 356ENTRY(cpu_arm922_set_pte_ext)
357#ifdef CONFIG_MMU 357#ifdef CONFIG_MMU
358 str r1, [r0], #-2048 @ linux version 358 armv3_set_pte_ext
359
360 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
361
362 bic r2, r1, #PTE_SMALL_AP_MASK
363 bic r2, r2, #PTE_TYPE_MASK
364 orr r2, r2, #PTE_TYPE_SMALL
365
366 tst r1, #L_PTE_USER @ User?
367 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
368
369 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
370 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
371
372 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
373 movne r2, #0
374
375#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
376 eor r3, r2, #0x0a @ C & small page?
377 tst r3, #0x0b
378 biceq r2, r2, #4
379#endif
380 str r2, [r0] @ hardware version
381 mov r0, r0 359 mov r0, r0
382 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 360 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
383 mcr p15, 0, r0, c7, c10, 4 @ drain WB 361 mcr p15, 0, r0, c7, c10, 4 @ drain WB
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index d045812f3399..2724526d89c1 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -52,7 +52,7 @@
52#include <linux/linkage.h> 52#include <linux/linkage.h>
53#include <linux/init.h> 53#include <linux/init.h>
54#include <asm/assembler.h> 54#include <asm/assembler.h>
55#include <asm/elf.h> 55#include <asm/hwcap.h>
56#include <asm/pgtable-hwdef.h> 56#include <asm/pgtable-hwdef.h>
57#include <asm/pgtable.h> 57#include <asm/pgtable.h>
58#include <asm/page.h> 58#include <asm/page.h>
@@ -398,29 +398,7 @@ ENTRY(cpu_arm925_switch_mm)
398 .align 5 398 .align 5
399ENTRY(cpu_arm925_set_pte_ext) 399ENTRY(cpu_arm925_set_pte_ext)
400#ifdef CONFIG_MMU 400#ifdef CONFIG_MMU
401 str r1, [r0], #-2048 @ linux version 401 armv3_set_pte_ext
402
403 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
404
405 bic r2, r1, #PTE_SMALL_AP_MASK
406 bic r2, r2, #PTE_TYPE_MASK
407 orr r2, r2, #PTE_TYPE_SMALL
408
409 tst r1, #L_PTE_USER @ User?
410 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
411
412 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
413 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
414
415 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
416 movne r2, #0
417
418#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
419 eor r3, r2, #0x0a @ C & small page?
420 tst r3, #0x0b
421 biceq r2, r2, #4
422#endif
423 str r2, [r0] @ hardware version
424 mov r0, r0 402 mov r0, r0
425#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 403#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
426 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 404 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 4cd33169a7c9..54466937bff9 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -28,7 +28,7 @@
28#include <linux/linkage.h> 28#include <linux/linkage.h>
29#include <linux/init.h> 29#include <linux/init.h>
30#include <asm/assembler.h> 30#include <asm/assembler.h>
31#include <asm/elf.h> 31#include <asm/hwcap.h>
32#include <asm/pgtable-hwdef.h> 32#include <asm/pgtable-hwdef.h>
33#include <asm/pgtable.h> 33#include <asm/pgtable.h>
34#include <asm/page.h> 34#include <asm/page.h>
@@ -359,29 +359,7 @@ ENTRY(cpu_arm926_switch_mm)
359 .align 5 359 .align 5
360ENTRY(cpu_arm926_set_pte_ext) 360ENTRY(cpu_arm926_set_pte_ext)
361#ifdef CONFIG_MMU 361#ifdef CONFIG_MMU
362 str r1, [r0], #-2048 @ linux version 362 armv3_set_pte_ext
363
364 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
365
366 bic r2, r1, #PTE_SMALL_AP_MASK
367 bic r2, r2, #PTE_TYPE_MASK
368 orr r2, r2, #PTE_TYPE_SMALL
369
370 tst r1, #L_PTE_USER @ User?
371 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
372
373 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
374 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
375
376 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
377 movne r2, #0
378
379#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
380 eor r3, r2, #0x0a @ C & small page?
381 tst r3, #0x0b
382 biceq r2, r2, #4
383#endif
384 str r2, [r0] @ hardware version
385 mov r0, r0 363 mov r0, r0
386#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 364#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
387 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 365 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index 551244d5ca19..f595117caf55 100644
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -11,7 +11,7 @@
11#include <linux/linkage.h> 11#include <linux/linkage.h>
12#include <linux/init.h> 12#include <linux/init.h>
13#include <asm/assembler.h> 13#include <asm/assembler.h>
14#include <asm/elf.h> 14#include <asm/hwcap.h>
15#include <asm/pgtable-hwdef.h> 15#include <asm/pgtable-hwdef.h>
16#include <asm/pgtable.h> 16#include <asm/pgtable.h>
17#include <asm/ptrace.h> 17#include <asm/ptrace.h>
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index 6168c6160dee..e03f6ff1fb26 100644
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -13,7 +13,7 @@
13#include <linux/linkage.h> 13#include <linux/linkage.h>
14#include <linux/init.h> 14#include <linux/init.h>
15#include <asm/assembler.h> 15#include <asm/assembler.h>
16#include <asm/elf.h> 16#include <asm/hwcap.h>
17#include <asm/pgtable-hwdef.h> 17#include <asm/pgtable-hwdef.h>
18#include <asm/pgtable.h> 18#include <asm/pgtable.h>
19#include <asm/ptrace.h> 19#include <asm/ptrace.h>
diff --git a/arch/arm/mm/proc-arm9tdmi.S b/arch/arm/mm/proc-arm9tdmi.S
index c85c1f50e396..be6c11d2b3fb 100644
--- a/arch/arm/mm/proc-arm9tdmi.S
+++ b/arch/arm/mm/proc-arm9tdmi.S
@@ -12,7 +12,7 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <asm/assembler.h> 13#include <asm/assembler.h>
14#include <asm/asm-offsets.h> 14#include <asm/asm-offsets.h>
15#include <asm/elf.h> 15#include <asm/hwcap.h>
16#include <asm/pgtable-hwdef.h> 16#include <asm/pgtable-hwdef.h>
17#include <asm/pgtable.h> 17#include <asm/pgtable.h>
18#include <asm/ptrace.h> 18#include <asm/ptrace.h>
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index f2e5884c513a..2b8bb383755e 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -22,7 +22,7 @@
22#include <linux/linkage.h> 22#include <linux/linkage.h>
23#include <linux/init.h> 23#include <linux/init.h>
24#include <asm/assembler.h> 24#include <asm/assembler.h>
25#include <asm/elf.h> 25#include <asm/hwcap.h>
26#include <asm/pgtable-hwdef.h> 26#include <asm/pgtable-hwdef.h>
27#include <asm/pgtable.h> 27#include <asm/pgtable.h>
28#include <asm/page.h> 28#include <asm/page.h>
@@ -446,24 +446,7 @@ ENTRY(cpu_feroceon_switch_mm)
446 .align 5 446 .align 5
447ENTRY(cpu_feroceon_set_pte_ext) 447ENTRY(cpu_feroceon_set_pte_ext)
448#ifdef CONFIG_MMU 448#ifdef CONFIG_MMU
449 str r1, [r0], #-2048 @ linux version 449 armv3_set_pte_ext wc_disable=0
450
451 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
452
453 bic r2, r1, #PTE_SMALL_AP_MASK
454 bic r2, r2, #PTE_TYPE_MASK
455 orr r2, r2, #PTE_TYPE_SMALL
456
457 tst r1, #L_PTE_USER @ User?
458 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
459
460 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
461 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
462
463 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
464 movne r2, #0
465
466 str r2, [r0] @ hardware version
467 mov r0, r0 450 mov r0, r0
468 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 451 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
469#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH) 452#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index b13150052a76..54b1f721dec8 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -71,3 +71,173 @@
71 mov \reg, #16 @ size offset 71 mov \reg, #16 @ size offset
72 mov \reg, \reg, lsl \tmp @ actual cache line size 72 mov \reg, \reg, lsl \tmp @ actual cache line size
73 .endm 73 .endm
74
75
76/*
77 * Sanity check the PTE configuration for the code below - which makes
78 * certain assumptions about how these bits are layed out.
79 */
80#if L_PTE_SHARED != PTE_EXT_SHARED
81#error PTE shared bit mismatch
82#endif
83#if L_PTE_BUFFERABLE != PTE_BUFFERABLE
84#error PTE bufferable bit mismatch
85#endif
86#if L_PTE_CACHEABLE != PTE_CACHEABLE
87#error PTE cacheable bit mismatch
88#endif
89#if (L_PTE_EXEC+L_PTE_USER+L_PTE_WRITE+L_PTE_DIRTY+L_PTE_YOUNG+\
90 L_PTE_FILE+L_PTE_PRESENT) > L_PTE_SHARED
91#error Invalid Linux PTE bit settings
92#endif
93
94/*
95 * The ARMv6 and ARMv7 set_pte_ext translation function.
96 *
97 * Permission translation:
98 * YUWD APX AP1 AP0 SVC User
99 * 0xxx 0 0 0 no acc no acc
100 * 100x 1 0 1 r/o no acc
101 * 10x0 1 0 1 r/o no acc
102 * 1011 0 0 1 r/w no acc
103 * 110x 0 1 0 r/w r/o
104 * 11x0 0 1 0 r/w r/o
105 * 1111 0 1 1 r/w r/w
106 */
107 .macro armv6_mt_table pfx
108\pfx\()_mt_table:
109 .long 0x00 @ L_PTE_MT_UNCACHED
110 .long PTE_EXT_TEX(1) @ L_PTE_MT_BUFFERABLE
111 .long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
112 .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
113 .long PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED
114 .long 0x00 @ unused
115 .long 0x00 @ L_PTE_MT_MINICACHE (not present)
116 .long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC
117 .long 0x00 @ unused
118 .long PTE_EXT_TEX(1) @ L_PTE_MT_DEV_WC
119 .long 0x00 @ unused
120 .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
121 .long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED
122 .long 0x00 @ unused
123 .long 0x00 @ unused
124 .long 0x00 @ unused
125 .endm
126
127 .macro armv6_set_pte_ext pfx
128 str r1, [r0], #-2048 @ linux version
129
130 bic r3, r1, #0x000003fc
131 bic r3, r3, #PTE_TYPE_MASK
132 orr r3, r3, r2
133 orr r3, r3, #PTE_EXT_AP0 | 2
134
135 adr ip, \pfx\()_mt_table
136 and r2, r1, #L_PTE_MT_MASK
137 ldr r2, [ip, r2]
138
139 tst r1, #L_PTE_WRITE
140 tstne r1, #L_PTE_DIRTY
141 orreq r3, r3, #PTE_EXT_APX
142
143 tst r1, #L_PTE_USER
144 orrne r3, r3, #PTE_EXT_AP1
145 tstne r3, #PTE_EXT_APX
146 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
147
148 tst r1, #L_PTE_EXEC
149 orreq r3, r3, #PTE_EXT_XN
150
151 orr r3, r3, r2
152
153 tst r1, #L_PTE_YOUNG
154 tstne r1, #L_PTE_PRESENT
155 moveq r3, #0
156
157 str r3, [r0]
158 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
159 .endm
160
161
162/*
163 * The ARMv3, ARMv4 and ARMv5 set_pte_ext translation function,
164 * covering most CPUs except Xscale and Xscale 3.
165 *
166 * Permission translation:
167 * YUWD AP SVC User
168 * 0xxx 0x00 no acc no acc
169 * 100x 0x00 r/o no acc
170 * 10x0 0x00 r/o no acc
171 * 1011 0x55 r/w no acc
172 * 110x 0xaa r/w r/o
173 * 11x0 0xaa r/w r/o
174 * 1111 0xff r/w r/w
175 */
176 .macro armv3_set_pte_ext wc_disable=1
177 str r1, [r0], #-2048 @ linux version
178
179 eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
180
181 bic r2, r1, #PTE_SMALL_AP_MASK @ keep C, B bits
182 bic r2, r2, #PTE_TYPE_MASK
183 orr r2, r2, #PTE_TYPE_SMALL
184
185 tst r3, #L_PTE_USER @ user?
186 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
187
188 tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ write and dirty?
189 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
190
191 tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ present and young?
192 movne r2, #0
193
194 .if \wc_disable
195#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
196 tst r2, #PTE_CACHEABLE
197 bicne r2, r2, #PTE_BUFFERABLE
198#endif
199 .endif
200 str r2, [r0] @ hardware version
201 .endm
202
203
204/*
205 * Xscale set_pte_ext translation, split into two halves to cope
206 * with work-arounds. r3 must be preserved by code between these
207 * two macros.
208 *
209 * Permission translation:
210 * YUWD AP SVC User
211 * 0xxx 00 no acc no acc
212 * 100x 00 r/o no acc
213 * 10x0 00 r/o no acc
214 * 1011 01 r/w no acc
215 * 110x 10 r/w r/o
216 * 11x0 10 r/w r/o
217 * 1111 11 r/w r/w
218 */
219 .macro xscale_set_pte_ext_prologue
220 str r1, [r0], #-2048 @ linux version
221
222 eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
223
224 bic r2, r1, #PTE_SMALL_AP_MASK @ keep C, B bits
225 orr r2, r2, #PTE_TYPE_EXT @ extended page
226
227 tst r3, #L_PTE_USER @ user?
228 orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w
229
230 tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ write and dirty?
231 orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w
232 @ combined with user -> user r/w
233 .endm
234
235 .macro xscale_set_pte_ext_epilogue
236 tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ present and young?
237 movne r2, #0 @ no -> fault
238
239 str r2, [r0] @ hardware version
240 mov ip, #0
241 mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
242 mcr p15, 0, ip, c7, c10, 4 @ data write barrier
243 .endm
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index bbe10576c861..90a7e5279f29 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -17,7 +17,7 @@
17#include <linux/init.h> 17#include <linux/init.h>
18#include <asm/assembler.h> 18#include <asm/assembler.h>
19#include <asm/asm-offsets.h> 19#include <asm/asm-offsets.h>
20#include <asm/elf.h> 20#include <asm/hwcap.h>
21#include <mach/hardware.h> 21#include <mach/hardware.h>
22#include <asm/pgtable-hwdef.h> 22#include <asm/pgtable-hwdef.h>
23#include <asm/pgtable.h> 23#include <asm/pgtable.h>
@@ -153,24 +153,7 @@ ENTRY(cpu_sa110_switch_mm)
153 .align 5 153 .align 5
154ENTRY(cpu_sa110_set_pte_ext) 154ENTRY(cpu_sa110_set_pte_ext)
155#ifdef CONFIG_MMU 155#ifdef CONFIG_MMU
156 str r1, [r0], #-2048 @ linux version 156 armv3_set_pte_ext wc_disable=0
157
158 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
159
160 bic r2, r1, #PTE_SMALL_AP_MASK
161 bic r2, r2, #PTE_TYPE_MASK
162 orr r2, r2, #PTE_TYPE_SMALL
163
164 tst r1, #L_PTE_USER @ User?
165 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
166
167 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
168 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
169
170 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
171 movne r2, #0
172
173 str r2, [r0] @ hardware version
174 mov r0, r0 157 mov r0, r0
175 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 158 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
176 mcr p15, 0, r0, c7, c10, 4 @ drain WB 159 mcr p15, 0, r0, c7, c10, 4 @ drain WB
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 871ba018252e..451e2d953e2a 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -22,7 +22,7 @@
22#include <linux/init.h> 22#include <linux/init.h>
23#include <asm/assembler.h> 23#include <asm/assembler.h>
24#include <asm/asm-offsets.h> 24#include <asm/asm-offsets.h>
25#include <asm/elf.h> 25#include <asm/hwcap.h>
26#include <mach/hardware.h> 26#include <mach/hardware.h>
27#include <asm/pgtable-hwdef.h> 27#include <asm/pgtable-hwdef.h>
28#include <asm/pgtable.h> 28#include <asm/pgtable.h>
@@ -166,24 +166,7 @@ ENTRY(cpu_sa1100_switch_mm)
166 .align 5 166 .align 5
167ENTRY(cpu_sa1100_set_pte_ext) 167ENTRY(cpu_sa1100_set_pte_ext)
168#ifdef CONFIG_MMU 168#ifdef CONFIG_MMU
169 str r1, [r0], #-2048 @ linux version 169 armv3_set_pte_ext wc_disable=0
170
171 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
172
173 bic r2, r1, #PTE_SMALL_AP_MASK
174 bic r2, r2, #PTE_TYPE_MASK
175 orr r2, r2, #PTE_TYPE_SMALL
176
177 tst r1, #L_PTE_USER @ User?
178 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
179
180 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
181 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
182
183 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
184 movne r2, #0
185
186 str r2, [r0] @ hardware version
187 mov r0, r0 170 mov r0, r0
188 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 171 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
189 mcr p15, 0, r0, c7, c10, 4 @ drain WB 172 mcr p15, 0, r0, c7, c10, 4 @ drain WB
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 5702ec58b2a2..294943b85973 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -13,7 +13,7 @@
13#include <linux/linkage.h> 13#include <linux/linkage.h>
14#include <asm/assembler.h> 14#include <asm/assembler.h>
15#include <asm/asm-offsets.h> 15#include <asm/asm-offsets.h>
16#include <asm/elf.h> 16#include <asm/hwcap.h>
17#include <asm/pgtable-hwdef.h> 17#include <asm/pgtable-hwdef.h>
18#include <asm/pgtable.h> 18#include <asm/pgtable.h>
19 19
@@ -114,46 +114,12 @@ ENTRY(cpu_v6_switch_mm)
114 * (hardware version is stored at -1024 bytes) 114 * (hardware version is stored at -1024 bytes)
115 * - pte - PTE value to store 115 * - pte - PTE value to store
116 * - ext - value for extended PTE bits 116 * - ext - value for extended PTE bits
117 *
118 * Permissions:
119 * YUWD APX AP1 AP0 SVC User
120 * 0xxx 0 0 0 no acc no acc
121 * 100x 1 0 1 r/o no acc
122 * 10x0 1 0 1 r/o no acc
123 * 1011 0 0 1 r/w no acc
124 * 110x 0 1 0 r/w r/o
125 * 11x0 0 1 0 r/w r/o
126 * 1111 0 1 1 r/w r/w
127 */ 117 */
118 armv6_mt_table cpu_v6
119
128ENTRY(cpu_v6_set_pte_ext) 120ENTRY(cpu_v6_set_pte_ext)
129#ifdef CONFIG_MMU 121#ifdef CONFIG_MMU
130 str r1, [r0], #-2048 @ linux version 122 armv6_set_pte_ext cpu_v6
131
132 bic r3, r1, #0x000003f0
133 bic r3, r3, #0x00000003
134 orr r3, r3, r2
135 orr r3, r3, #PTE_EXT_AP0 | 2
136
137 tst r1, #L_PTE_WRITE
138 tstne r1, #L_PTE_DIRTY
139 orreq r3, r3, #PTE_EXT_APX
140
141 tst r1, #L_PTE_USER
142 orrne r3, r3, #PTE_EXT_AP1
143 tstne r3, #PTE_EXT_APX
144 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
145
146 tst r1, #L_PTE_YOUNG
147 biceq r3, r3, #PTE_EXT_APX | PTE_EXT_AP_MASK
148
149 tst r1, #L_PTE_EXEC
150 orreq r3, r3, #PTE_EXT_XN
151
152 tst r1, #L_PTE_PRESENT
153 moveq r3, #0
154
155 str r3, [r0]
156 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
157#endif 123#endif
158 mov pc, lr 124 mov pc, lr
159 125
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index a67e26f3dce2..34e424041927 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -12,7 +12,7 @@
12#include <linux/linkage.h> 12#include <linux/linkage.h>
13#include <asm/assembler.h> 13#include <asm/assembler.h>
14#include <asm/asm-offsets.h> 14#include <asm/asm-offsets.h>
15#include <asm/elf.h> 15#include <asm/hwcap.h>
16#include <asm/pgtable-hwdef.h> 16#include <asm/pgtable-hwdef.h>
17#include <asm/pgtable.h> 17#include <asm/pgtable.h>
18 18
@@ -105,26 +105,19 @@ ENDPROC(cpu_v7_switch_mm)
105 * (hardware version is stored at -1024 bytes) 105 * (hardware version is stored at -1024 bytes)
106 * - pte - PTE value to store 106 * - pte - PTE value to store
107 * - ext - value for extended PTE bits 107 * - ext - value for extended PTE bits
108 *
109 * Permissions:
110 * YUWD APX AP1 AP0 SVC User
111 * 0xxx 0 0 0 no acc no acc
112 * 100x 1 0 1 r/o no acc
113 * 10x0 1 0 1 r/o no acc
114 * 1011 0 0 1 r/w no acc
115 * 110x 0 1 0 r/w r/o
116 * 11x0 0 1 0 r/w r/o
117 * 1111 0 1 1 r/w r/w
118 */ 108 */
119ENTRY(cpu_v7_set_pte_ext) 109ENTRY(cpu_v7_set_pte_ext)
120#ifdef CONFIG_MMU 110#ifdef CONFIG_MMU
121 str r1, [r0], #-2048 @ linux version 111 str r1, [r0], #-2048 @ linux version
122 112
123 bic r3, r1, #0x000003f0 113 bic r3, r1, #0x000003f0
124 bic r3, r3, #0x00000003 114 bic r3, r3, #PTE_TYPE_MASK
125 orr r3, r3, r2 115 orr r3, r3, r2
126 orr r3, r3, #PTE_EXT_AP0 | 2 116 orr r3, r3, #PTE_EXT_AP0 | 2
127 117
118 tst r2, #1 << 4
119 orrne r3, r3, #PTE_EXT_TEX(1)
120
128 tst r1, #L_PTE_WRITE 121 tst r1, #L_PTE_WRITE
129 tstne r1, #L_PTE_DIRTY 122 tstne r1, #L_PTE_DIRTY
130 orreq r3, r3, #PTE_EXT_APX 123 orreq r3, r3, #PTE_EXT_APX
@@ -134,13 +127,11 @@ ENTRY(cpu_v7_set_pte_ext)
134 tstne r3, #PTE_EXT_APX 127 tstne r3, #PTE_EXT_APX
135 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0 128 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
136 129
137 tst r1, #L_PTE_YOUNG
138 biceq r3, r3, #PTE_EXT_APX | PTE_EXT_AP_MASK
139
140 tst r1, #L_PTE_EXEC 130 tst r1, #L_PTE_EXEC
141 orreq r3, r3, #PTE_EXT_XN 131 orreq r3, r3, #PTE_EXT_XN
142 132
143 tst r1, #L_PTE_PRESENT 133 tst r1, #L_PTE_YOUNG
134 tstne r1, #L_PTE_PRESENT
144 moveq r3, #0 135 moveq r3, #0
145 136
146 str r3, [r0] 137 str r3, [r0]
@@ -189,6 +180,10 @@ __v7_setup:
189 mov r10, #0x1f @ domains 0, 1 = manager 180 mov r10, #0x1f @ domains 0, 1 = manager
190 mcr p15, 0, r10, c3, c0, 0 @ load domain access register 181 mcr p15, 0, r10, c3, c0, 0 @ load domain access register
191#endif 182#endif
183 ldr r5, =0x40e040e0
184 ldr r6, =0xff0aa1a8
185 mcr p15, 0, r5, c10, c2, 0 @ write PRRR
186 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
192 adr r5, v7_crval 187 adr r5, v7_crval
193 ldmia r5, {r5, r6} 188 ldmia r5, {r5, r6}
194 mrc p15, 0, r0, c1, c0, 0 @ read control register 189 mrc p15, 0, r0, c1, c0, 0 @ read control register
@@ -205,7 +200,7 @@ ENDPROC(__v7_setup)
205 */ 200 */
206 .type v7_crval, #object 201 .type v7_crval, #object
207v7_crval: 202v7_crval:
208 crval clear=0x0120c302, mmuset=0x00c0387d, ucset=0x00c0187c 203 crval clear=0x0120c302, mmuset=0x10c0387d, ucset=0x00c0187c
209 204
210__v7_setup_stack: 205__v7_setup_stack:
211 .space 4 * 11 @ 11 registers 206 .space 4 * 11 @ 11 registers
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 7bd9e7197f60..04dc8b65401b 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -27,7 +27,7 @@
27#include <linux/linkage.h> 27#include <linux/linkage.h>
28#include <linux/init.h> 28#include <linux/init.h>
29#include <asm/assembler.h> 29#include <asm/assembler.h>
30#include <asm/elf.h> 30#include <asm/hwcap.h>
31#include <mach/hardware.h> 31#include <mach/hardware.h>
32#include <asm/pgtable.h> 32#include <asm/pgtable.h>
33#include <asm/pgtable-hwdef.h> 33#include <asm/pgtable-hwdef.h>
@@ -345,38 +345,38 @@ ENTRY(cpu_xsc3_switch_mm)
345 * cpu_xsc3_set_pte_ext(ptep, pte, ext) 345 * cpu_xsc3_set_pte_ext(ptep, pte, ext)
346 * 346 *
347 * Set a PTE and flush it out 347 * Set a PTE and flush it out
348 *
349 */ 348 */
349cpu_xsc3_mt_table:
350 .long 0x00 @ L_PTE_MT_UNCACHED
351 .long PTE_EXT_TEX(1) @ L_PTE_MT_BUFFERABLE
352 .long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
353 .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
354 .long PTE_EXT_TEX(1) | PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED
355 .long 0x00 @ unused
356 .long 0x00 @ L_PTE_MT_MINICACHE (not present)
357 .long PTE_EXT_TEX(5) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC (not present?)
358 .long 0x00 @ unused
359 .long PTE_EXT_TEX(1) @ L_PTE_MT_DEV_WC
360 .long 0x00 @ unused
361 .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
362 .long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED
363 .long 0x00 @ unused
364 .long 0x00 @ unused
365 .long 0x00 @ unused
366
350 .align 5 367 .align 5
351ENTRY(cpu_xsc3_set_pte_ext) 368ENTRY(cpu_xsc3_set_pte_ext)
352 str r1, [r0], #-2048 @ linux version 369 xscale_set_pte_ext_prologue
353 370
354 bic r2, r1, #0xff0 @ keep C, B bits
355 orr r2, r2, #PTE_TYPE_EXT @ extended page
356 tst r1, #L_PTE_SHARED @ shared? 371 tst r1, #L_PTE_SHARED @ shared?
357 orrne r2, r2, #0x200 372 and r1, r1, #L_PTE_MT_MASK
358 373 adr ip, cpu_xsc3_mt_table
359 eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 374 ldr ip, [ip, r1]
360 375 orrne r2, r2, #PTE_EXT_COHERENT @ interlock: mask in coherent bit
361 tst r3, #L_PTE_USER @ user? 376 bic r2, r2, #0x0c @ clear old C,B bits
362 orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w 377 orr r2, r2, ip
363 378
364 tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ write and dirty? 379 xscale_set_pte_ext_epilogue
365 orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w
366 @ combined with user -> user r/w
367
368 @ If it's cacheable, it needs to be in L2 also.
369 eor ip, r1, #L_PTE_CACHEABLE
370 tst ip, #L_PTE_CACHEABLE
371 orreq r2, r2, #PTE_EXT_TEX(0x5)
372
373 tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ present and young?
374 movne r2, #0 @ no -> fault
375
376 str r2, [r0] @ hardware version
377 mov ip, #0
378 mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
379 mcr p15, 0, ip, c7, c10, 4 @ data write barrier
380 mov pc, lr 380 mov pc, lr
381 381
382 .ltorg 382 .ltorg
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 2dd85273976f..0cce37b93937 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -23,7 +23,7 @@
23#include <linux/linkage.h> 23#include <linux/linkage.h>
24#include <linux/init.h> 24#include <linux/init.h>
25#include <asm/assembler.h> 25#include <asm/assembler.h>
26#include <asm/elf.h> 26#include <asm/hwcap.h>
27#include <asm/pgtable.h> 27#include <asm/pgtable.h>
28#include <asm/pgtable-hwdef.h> 28#include <asm/pgtable-hwdef.h>
29#include <asm/page.h> 29#include <asm/page.h>
@@ -406,8 +406,6 @@ ENTRY(cpu_xscale_dcache_clean_area)
406 406
407/* =============================== PageTable ============================== */ 407/* =============================== PageTable ============================== */
408 408
409#define PTE_CACHE_WRITE_ALLOCATE 0
410
411/* 409/*
412 * cpu_xscale_switch_mm(pgd) 410 * cpu_xscale_switch_mm(pgd)
413 * 411 *
@@ -431,56 +429,42 @@ ENTRY(cpu_xscale_switch_mm)
431 * 429 *
432 * Errata 40: must set memory to write-through for user read-only pages. 430 * Errata 40: must set memory to write-through for user read-only pages.
433 */ 431 */
432cpu_xscale_mt_table:
433 .long 0x00 @ L_PTE_MT_UNCACHED
434 .long PTE_BUFFERABLE @ L_PTE_MT_BUFFERABLE
435 .long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
436 .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
437 .long PTE_EXT_TEX(1) | PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED
438 .long 0x00 @ unused
439 .long PTE_EXT_TEX(1) | PTE_CACHEABLE @ L_PTE_MT_MINICACHE
440 .long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC
441 .long 0x00 @ unused
442 .long PTE_BUFFERABLE @ L_PTE_MT_DEV_WC
443 .long 0x00 @ unused
444 .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
445 .long 0x00 @ L_PTE_MT_DEV_NONSHARED
446 .long 0x00 @ unused
447 .long 0x00 @ unused
448 .long 0x00 @ unused
449
434 .align 5 450 .align 5
435ENTRY(cpu_xscale_set_pte_ext) 451ENTRY(cpu_xscale_set_pte_ext)
436 str r1, [r0], #-2048 @ linux version 452 xscale_set_pte_ext_prologue
437
438 bic r2, r1, #0xff0
439 orr r2, r2, #PTE_TYPE_EXT @ extended page
440
441 eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
442
443 tst r3, #L_PTE_USER @ User?
444 orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w
445
446 tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
447 orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w
448 @ combined with user -> user r/w
449
450 @
451 @ Handle the X bit. We want to set this bit for the minicache
452 @ (U = E = B = W = 0, C = 1) or when write allocate is enabled,
453 @ and we have a writeable, cacheable region. If we ignore the
454 @ U and E bits, we can allow user space to use the minicache as
455 @ well.
456 @
457 @ X = (C & ~W & ~B) | (C & W & B & write_allocate)
458 @
459 eor ip, r1, #L_PTE_CACHEABLE
460 tst ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
461#if PTE_CACHE_WRITE_ALLOCATE
462 eorne ip, r1, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
463 tstne ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
464#endif
465 orreq r2, r2, #PTE_EXT_TEX(1)
466 453
467 @ 454 @
468 @ Erratum 40: The B bit must be cleared for a user read-only 455 @ Erratum 40: must set memory to write-through for user read-only pages
469 @ cacheable page.
470 @
471 @ B = B & ~(U & C & ~W)
472 @ 456 @
473 and ip, r1, #L_PTE_USER | L_PTE_WRITE | L_PTE_CACHEABLE 457 and ip, r1, #(L_PTE_MT_MASK | L_PTE_USER | L_PTE_WRITE) & ~(4 << 2)
474 teq ip, #L_PTE_USER | L_PTE_CACHEABLE 458 teq ip, #L_PTE_MT_WRITEBACK | L_PTE_USER
475 biceq r2, r2, #PTE_BUFFERABLE
476 459
477 tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young? 460 moveq r1, #L_PTE_MT_WRITETHROUGH
478 movne r2, #0 @ no -> fault 461 and r1, r1, #L_PTE_MT_MASK
462 adr ip, cpu_xscale_mt_table
463 ldr ip, [ip, r1]
464 bic r2, r2, #0x0c
465 orr r2, r2, ip
479 466
480 str r2, [r0] @ hardware version 467 xscale_set_pte_ext_epilogue
481 mov ip, #0
482 mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
483 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
484 mov pc, lr 468 mov pc, lr
485 469
486 470
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-22 18:22:59 -0400