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authorWill Deacon <will.deacon@arm.com>2012-09-01 00:22:12 -0400
committerWill Deacon <will.deacon@arm.com>2012-11-09 09:13:20 -0500
commit26ffd0d43b186b0d5186354da8714a1c2d360df0 (patch)
tree405c83d298530b65bb64630da52cfb368927691a /arch/arm/mm
parentdbf62d50067e55a782583fe53c3d2a3d98b1f6f3 (diff)
ARM: mm: introduce present, faulting entries for PAGE_NONE
PROT_NONE mappings apply the page protection attributes defined by _P000 which translate to PAGE_NONE for ARM. These attributes specify an XN, RDONLY pte that is inaccessible to userspace. However, on kernels configured without support for domains, such a pte *is* accessible to the kernel and can be read via get_user, allowing tasks to read PROT_NONE pages via syscalls such as read/write over a pipe. This patch introduces a new software pte flag, L_PTE_NONE, that is set to identify faulting, present entries. Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm/mm')
-rw-r--r--arch/arm/mm/proc-macros.S4
-rw-r--r--arch/arm/mm/proc-v7-2level.S4
-rw-r--r--arch/arm/mm/proc-v7-3level.S3
3 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index b29a2265af01..eb6aa73bc8b7 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -167,6 +167,10 @@
167 tst r1, #L_PTE_YOUNG 167 tst r1, #L_PTE_YOUNG
168 tstne r1, #L_PTE_PRESENT 168 tstne r1, #L_PTE_PRESENT
169 moveq r3, #0 169 moveq r3, #0
170#ifndef CONFIG_CPU_USE_DOMAINS
171 tstne r1, #L_PTE_NONE
172 movne r3, #0
173#endif
170 174
171 str r3, [r0] 175 str r3, [r0]
172 mcr p15, 0, r0, c7, c10, 1 @ flush_pte 176 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S
index e755e9f8d1b4..6d98c13ab827 100644
--- a/arch/arm/mm/proc-v7-2level.S
+++ b/arch/arm/mm/proc-v7-2level.S
@@ -101,6 +101,10 @@ ENTRY(cpu_v7_set_pte_ext)
101 101
102 tst r1, #L_PTE_YOUNG 102 tst r1, #L_PTE_YOUNG
103 tstne r1, #L_PTE_VALID 103 tstne r1, #L_PTE_VALID
104#ifndef CONFIG_CPU_USE_DOMAINS
105 eorne r1, r1, #L_PTE_NONE
106 tstne r1, #L_PTE_NONE
107#endif
104 moveq r3, #0 108 moveq r3, #0
105 109
106 ARM( str r3, [r0, #2048]! ) 110 ARM( str r3, [r0, #2048]! )
diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index d23d067e1904..7b56386f9496 100644
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -67,6 +67,9 @@ ENTRY(cpu_v7_set_pte_ext)
67#ifdef CONFIG_MMU 67#ifdef CONFIG_MMU
68 tst r2, #L_PTE_VALID 68 tst r2, #L_PTE_VALID
69 beq 1f 69 beq 1f
70 tst r3, #1 << (57 - 32) @ L_PTE_NONE
71 bicne r2, #L_PTE_VALID
72 bne 1f
70 tst r3, #1 << (55 - 32) @ L_PTE_DIRTY 73 tst r3, #1 << (55 - 32) @ L_PTE_DIRTY
71 orreq r2, #L_PTE_RDONLY 74 orreq r2, #L_PTE_RDONLY
721: strd r2, r3, [r0] 751: strd r2, r3, [r0]