diff options
author | Nicolas Pitre <nico@org.rmk.(none)> | 2005-05-12 14:27:12 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2005-05-12 14:27:12 -0400 |
commit | 70489c88d0b7e5820ac37a039a910bb396e2a4e3 (patch) | |
tree | 47f5ad9729469cad40c926af4961611208bdfdc1 /arch/arm/mm | |
parent | d7def6c22dfa9f32b3d9e5546a7a6a90c644ff5f (diff) |
[PATCH] ARM: 2680/1: refine TLS reg availability some more again
Patch from Nicolas Pitre
Not all ARMv6 processors implement the TLS register.
Signed-off-by: Nicolas Pitre
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm')
-rw-r--r-- | arch/arm/mm/Kconfig | 21 |
1 files changed, 10 insertions, 11 deletions
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 07646d25e265..48bac7da8c70 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig | |||
@@ -412,21 +412,20 @@ config CPU_BPREDICT_DISABLE | |||
412 | 412 | ||
413 | config TLS_REG_EMUL | 413 | config TLS_REG_EMUL |
414 | bool | 414 | bool |
415 | default y if (SMP || CPU_32v6) && (CPU_32v5 || CPU_32v4 || CPU_32v3) | 415 | default y if SMP && (CPU_32v5 || CPU_32v4 || CPU_32v3) |
416 | help | 416 | help |
417 | We might be running on an ARMv6+ processor which should have the TLS | 417 | An SMP system using a pre-ARMv6 processor (there are apparently |
418 | register but for some reason we can't use it, or maybe an SMP system | 418 | a few prototypes like that in existence) and therefore access to |
419 | using a pre-ARMv6 processor (there are apparently a few prototypes | 419 | that required register must be emulated. |
420 | like that in existence) and therefore access to that register must | ||
421 | be emulated. | ||
422 | 420 | ||
423 | config HAS_TLS_REG | 421 | config HAS_TLS_REG |
424 | bool | 422 | bool |
425 | depends on CPU_32v6 | 423 | depends on !TLS_REG_EMUL |
426 | default y if !TLS_REG_EMUL | 424 | default y if SMP || CPU_32v7 |
427 | help | 425 | help |
428 | This selects support for the CP15 thread register. | 426 | This selects support for the CP15 thread register. |
429 | It is defined to be available on ARMv6 or later. If a particular | 427 | It is defined to be available on some ARMv6 processors (including |
430 | ARMv6 or later CPU doesn't support it then it must include "select | 428 | all SMP capable ARMv6's) or later processors. User space may |
431 | TLS_REG_EMUL" along with its other characteristics. | 429 | assume directly accessing that register and always obtain the |
430 | expected value only on ARMv7 and above. | ||
432 | 431 | ||