[ARM] 2940/1: Fix BTB entry flush in arch/arm/mm/cache-v6.S

Patch from Gen FUKATSU

Invalidate BTB entry instruction flushes two instruction
at a time. Therefore this instruction should be done four
times after invalidate instruction cache line.

Signed-off-by: Gen Fukatsu
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 8 insertions, 1 deletions

diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index 85c10a71e7c6..72966d90e956 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -18,6 +18,7 @@
 #define HARVARD_CACHE
 #define CACHE_LINE_SIZE         32
 #define D_CACHE_LINE_SIZE       32
+#define BTB_FLUSH_SIZE          8
 
 /*
  *      v6_flush_cache_all()
@@ -98,7 +99,13 @@ ENTRY(v6_coherent_user_range)
         mcr     p15, 0, r0, c7, c5, 1           @ invalidate I line
 #endif
         mcr     p15, 0, r0, c7, c5, 7           @ invalidate BTB entry
-        add     r0, r0, #CACHE_LINE_SIZE
+        add     r0, r0, #BTB_FLUSH_SIZE
+        mcr     p15, 0, r0, c7, c5, 7           @ invalidate BTB entry
+        add     r0, r0, #BTB_FLUSH_SIZE
+        mcr     p15, 0, r0, c7, c5, 7           @ invalidate BTB entry
+        add     r0, r0, #BTB_FLUSH_SIZE
+        mcr     p15, 0, r0, c7, c5, 7           @ invalidate BTB entry
+        add     r0, r0, #BTB_FLUSH_SIZE
         cmp     r0, r1
         blo     1b
 #ifdef HARVARD_CACHE